:* If the instruction has more than one opcode, these opcodes are fetched.
:* the instruction is executed by the Z80.
:If maskable interrupts are disabled:
:* the Z80 will ignore the interrupt request and will not generate a interrupt acknowledge
Notes
:1. # The CPC+ does not support the full operation of Z80 interrupt mode 0. The CPC+ will only generate a single 8-bit interrupt-vector and will ignore additional opcode fetches for multi-byte instructions. :So, the operation of multi-byte instructions may be different with hardware designs that fully support interrupt mode 0. :Any signals that may be generated by the Z80 to fetch extra opcode bytes will be ignore. As a result, the observations I have seen may only apply to the CPC+ hardware design. :2. # As far as I know Z80 interrupt mode 0 has not been used in any programs. If it has been used in a CPC program, then it is likely to be unreliable when expansion peripherals are attached. If "FF" is read as the interrupt vector then this will have the same effect as interrupt mode 1. However, this will never work on the CPC+. When CPC+ features have not been enabled, the 8-bit interrupt vector will be "00" and not "FF" causing a "NOP" instruction to be executed. If CPC+ features have been enabled, and only standard interrupts are active, then a "LD B,n" instruction will be executed. It is not possible to program the CPC+ so that a 8-bit interrupt vector of "FF" is generated.