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Gate Array

64 bytes removed, 30 March
/* Register RMR2 (ASIC & Advanced ROM mapping) */
| 5 || 1
|-
| 4 || x || rowspan="2" |Lower ROM address and ASIC I/O page RMR addressing mode
|-
| 3 || x
|}
The lower {| class="wikitable"|+ RMR addressing modes!Bit 4!Bit 3!Lower ROM address and ![[Default I/O Port SummaryASIC|ASIC I/O page]] modes are:  |-Mode- ROM address ASIC I/O Page 00 |0|0|&0000-&3FFF |Disabled 01 |-|0|1|&4000-&7FFF |Disabled 10 |-|1|0|&8000-&BFFF |Disabled 11 |-|1|1|&0000-&3FFF |&4000-&7fff7FFF|}
The physical ROMs are also accessible as upper ROMs by using the [[Upper ROM Bank Number]] port and the RMR register.
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