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MOS 6502

539 bytes added, 2 April
/* Chip Variants */
== Pipelining ==
The 6502 CPU uses some sort We have to dispel the myth of pipeliningin the 6502. If an instruction does not store data we analyze its operation in memory on its last cyclehalf-cycles, the processor can fetch the opcode of the next we see that instruction while executing the last cycle. This execution is very primitive as the 6502 does not have an instruction cache nor even a prefetch queue. It relies on RAM tightly bound to hold all program informationmemory operations without any overlap between different instructions.
As an exampleEach instruction follows a rigid sequence of steps, with no ability to fetch the next instruction EOR #$FF truly takes 3 cycles:* On while executing the first cycle, current one. This means that the opcode $49 will be fetched* During the second cycle the processor decodes the opcode and fetches the parameter #$FF* On the third cycle, the processor will perform the operation and store the result CPU cannot prefetch opcodes or operands ahead of time in register A, but simultaneously it fetches the opcode for the next instructionway a pipelined architecture would.
This is If we invert our perspective and consider ϕ2 as the first half-cycle and ϕ1 as the second, it becomes evident why pipelining does not exist on the EOR instruction effectively takes only 2 cycles6502.
However, this pipelining only makes sense when looking at full cycles. If we break it down into half-cycles, there's no actual overlap. In fact, it's the other way around. If the previous instruction ends with a memory write, the CPU has to wait for a half-cycle before fetching being able to fetch the next instruction on the next ϕ2 half-cycle.
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== Adressing Modes ==
 
The 6502 uses only one addressing mode per instruction.
{| class="wikitable"
#Operand Fetch (if needed)
#Memory Read / I/O Read (if needed)
#ExecutionOperation
#Memory Write / I/O Write (if needed)
#At the end of every instruction, the IRQ (if the interrupt disable flag is clear) and NMI pins are checked.
 
As an example, let M[$42]=$80, M[$43]=$10 and Y=$F1. Then the instruction LDA ($42),Y will execute as follow, with ϕ2 as the first half-cycle and ϕ1 as the second half-cycle:
*T0: Fetch opcode $B1 (LDA (zp),Y) from memory then increment PC
*T1: Fetch operand byte $42 (zero page pointer address) then increment PC
*T2: Get low byte from zero page ($80) then increment the zero page address
*T3: Get high byte from next zero page location ($10) then add the Y register value ($F1) to $1080
*T4: Garbage fetch from memory address $1071 then handle page boundary crossing (since $1080 + $F1 crosses a page)
*T5: Read the value from memory address $1171 into the accumulator then no operation in the last half-cycle
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* On NMOS, an indirect JMP will behave unexpectedly when the indirect address crosses a page boundary, because the 6502 does not add the carry to calculate the address of the high byte. For example, JMP ($19FF) will use the contents of $19FF and $1900 for the JMP address. On CMOS, this issue was fixed, at the cost of 1 additional cycle. In our example, JMP ($19FF) will use the contents of $19FF and $2000 for the JMP address.
 
* Some instructions, particularly those involving branches or indexed addressing modes, incur an extra cycle if the processor has to cross a memory page boundary. This is problematic for time-sensitive code.
 
* Conditional jumps are only 8-bit relative. And unconditional jumps are only 16-bit absolute.
 
* ADC is the only command for addition. To perform an addition without carry, the carry flag must be cleared manually first. Same with SBC for subtract.
 
* The CLV (Clear Overflow Flag) instruction exist but not the SEV (Set Overflow Flag) instruction.
 
* The NOP instruction takes 2 full-cycles. This is the minimum amount of cycles an instruction can take. It is necessary because, while the instruction itself does nothing, it still has to increment the 16-bit PC register.
 
* The alternate NOPs are not created equal. Some have one- or two-byte operands (which they don't do anything with), and they take different amounts of time to execute.
 * The 6502 post-decrements on PHA 6502’s Decimal (BCD) mode automatically adjusts ADC and pre-increments on PLASBC results, while the Z80 pre-decrements on PUSH requires a DAA instruction after each BCD addition and post-increments on POP, making them behave in opposite wayssubtraction. 
* The 6502 uses only one addressing mode per instruction, while the Z80 can combine two different addressing modes within a single instruction.
* The 6502 post-decrements on PHA and pre-increments on PLA, while the Z80 pre-decrements on PUSH and post-increments on POP.
* The 6502 saves flags automatically during interrupts; while the Z80 requires PUSH AF and POP AF.
 
* The 6502’s Decimal (BCD) mode automatically adjusts ADC and SBC results, while the Z80 requires a DAA instruction after each BCD addition and subtraction.
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* The ROR instruction didn't exist in the very earliest (pre-1977) chips. See: [https://www.pagetable.com/?p=406 Measuring the ROR Bug in the Early MOS 6502]
* The 6502 core used inside the [[NES]] is missing the Decimal Mode feature. [https://archive.org/details/nes-programmers-reference-guide-by-electronic-arts-1989/ NES programmer's reference guide] [https://www.nesdev.org/NESDoc.pdf NESDoc] [https://www.nesdev.org/wiki/Mapper NES mappers] [https://problemkaputt.de/everynes.htm Noca$h's Everynes] [https://www.nesdev.org/wiki/Emulator_tests NES emulator tests] [https://tcrf.net/Category:Nintendo_Console_Testing_Software Official Nintendo testing software]
* The 6507 CPU, used in the [[Atari VCS]], has only 13 address lines. So it can only address 8KB instead of 64KB. It also lacks the IRQ and NMI interrupt lines. [https://youtu.be/qvpwf50a48E Atari VCS: The Ultimate Talk] [https://cdn.hackaday.io/files/1646277043401568/stella.pdf Stella programmer's guide] [https://www.atarimania.com/documents/stella_system_training_manual.pdf Stella system training manual] [https://problemkaputt.de/2k6specs.htm Noca$h's 2k6specs]
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