Changes
/* Patent */
Once the ASIC is unlocked, we get access to a new [[Gate Array]] register called RMR2. It is accessible in the same way as other Gate Array registers.
Locking the ASIC again doesn't disable any of its functionality, it just prevents you changing it. [https://www.cpcwiki.eu/forum/programming/asm-source-code/msg249856/#msg249856 Source]
<br>
ld hl,sequence
ld e,17
.seq
ld a,(hl)
dec e
jr nz,seq
ei
ret
<br>
= Optimized version versions =
The unlocking sequence can be reconstituted from simple bit operations instead of being stored in memory.
== In Z80 Assembler [[Madram]] version == It still uses some magic numbers.
<pre>
ld bc,#BCFF
out (c),c
out (c),0
ld hl,%1001000011101010
out (c),c
ld a,h:rlca:ld h,l:ld l,a
srl c:res 3,cxor c:and #88or :xor c
ld c,a
cp #4D
jr nz,.loop ld a,#CD ; a = #CD for unlock, another value for lockout (c),a : out (c),aei
ret
</pre>
== In Python [[Urusergi]] version == No magic numbers here.
<pre>
eiret</pre> == Algorithm == <pre>def unlock_asic(): b, c = 0xBC, 0xFF port_outout(b, 0xCDc) port_outout(b, 0xCD0) a = c while True: out(b, a) # a = (7 xor 4)765 (1 xor 0)321 a = ((a >> 1) & 0x77) | ((a ^ (a << 3)) & 0x80) | (((a << 2) ^ (a << 3)) & 0x08) if a == c: break
def port_outout(port, value): print(f"Port: {hex(port)}xx Out: {hex(value)}")
unlock_asic()
= Patent =
For one reason or another, Amstrad has patented the verification mechanism ([[Media:Patent GB2243701A.pdf|GB2243701A]]). The patent seems to focus on ''verifying'' (rather than on ''sending'') the sequence, so its legal use is a bit unclear.
According to [https://patents.google.com/patent/GB2243701A/en Google patents for GB2243701A] the patent was withdrawn on 1994-12-21. This means that this particular patent cannot be enforced.
<br>
[[Category:Programming]]
[[Category:CPC Plus]]
