Changes
CRTC
,/* VSYNC */
On all CRTCs, in both interlace modes, a mid-VSYNC is generated when VCC=R7 on the even field. The VSYNC pulse starts in the middle of the raster line, at HCC=R0/2.
As an exception, on CRTCs 3/4, if R7=0 then mid-VSYNC will instead occur on the odd field if R7=0.
=== PPI VSYNC ===
