Changes
/* Bus arbitration */
Note: On Amstrad Plus, the ASIC also has to handle DMA instruction fetch from RAM.
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== DRAM refresh ==
On Amstrad CPC, the Gate Array is responsible for the DRAM refresh instead of using the Z80 built-in DRAM refresh mechanism. The reason is that there can only be 3 DRAM access per microsecond.
The Z80 generates a maximum of one request per microsecond. The CPC also requires two memory accesses per microsecond for reading video data.
The CPC specs 4164-20 DRAMs. These require 330nS for a read or write cycle. The CPC also uses the optimised sequential CAS cycles to read the two video data bytes.
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