|}
The See the [[ASIC]] I/O page is defined as follows: {| class="wikitable"! ADDR! SIZE! POR! TYPE! MNEM! USE|-| 4000h || 100h || N || R/W || || Sprite 0 image data|-| 4100h || 100h || N || R/W || || Sprite 1 image data|-| ... || ... || ... || ... || ... || ...|-| 4F00h || 100h || N || R/W || || Sprite 15 image data|-|style="background:#efefef;" colspan="6"|''Block unused''|-| 6000h || 2 || N || R/W || X0 || Sprite 0 X position|-| 6002h || 2 || N || R/W || Y0 || Sprite 0 Y position|-| 6004h || 1 || Y || W || M0 || Sprite 0 magnification|-| 6005h || 3 || || || || (unused)|-| 6008h || 2 || N || R/W || X1 || Sprite 1 X position|-| 600Ah || 2 || N || R/W || Y1 || Sprite 1 Y position|-| 600Ch || 1 || Y || W || M1 || Sprite 1 magnification|-| 600Dh || 3 || || || || (unused)|-| ... || ... || ... || ... || ... || ...|-| 6078h || 2 || N || R/W || X15 || Sprite 15 X position|-| 607Ah || 2 || N || R/W || Y15 || Sprite 15 Y position|-| 607Ch || 1 || N || W || M15 || Sprite 15 magnification|-| 607Dh || 3 || || || || (unused)|-|style="background:#efefef;" colspan="6"|''Block unused''|-| 6400h || 2 || N || R/W || || Colour palette, pen 0|-| 6402h || 2 || N || R/W || || Colour palette, pen 1|-| ... || ... || ... || ... || ... || ...|-| 641Eh || 2 || N || R/W || || Colour palette, pen 15|-| 6420h || 2 || N || R/W || || Colour palette, border|-| 6422h || 2 || N || R/W || || Colour palette, sprite colour 1|-| 6424h || 2 || N || R/W || || Colour palette, sprite colour 2|-| ... || ... || ... || ... || ... || ...|-| 643Eh || 2 || N || R/W || || Colour palette, sprite colour 15|-|style="background:#efefef;" colspan="6"|''Block unused''|-| 6800h || 1 || Y || W || PRI || Programmable raster interrupt scan line|-| 6801h || 1 || Y || W || SPLT || Screen split scan line|-| 6802h || 2 || N || W || SSA || Screen split secondary start address|-| 6804h || 1 || Y || W || SSCR || Soft scroll control register|-| 6805h || 1 || N || W || IVR || Interrupt Vector (Bit 0 set to 1 on reset)|-| 6806h || 2 || || || || (unused)|-| 6808h || 1 || || R || ADC0 || Analogue input channel 0|-| 6809h || 1 || || R || ADC1 || Analogue input channel 1|-| 680Ah || 1 || || R || ADC2 || Analogue input channel 2|-| 680Bh || 1 || || R || ADC3 || Analogue input channel 3|-| 680Ch || 1 || || R || ADC4 || Analogue input channel 4|-| 680Dh || 1 || || R || ADC5 || Analogue input channel 5|-| 680Eh || 1 || || R || ADC6 || Analogue input channel 6|-| 680Fh || 1 || || R || ADC7 || Analogue input channel 7|-|style="background:#efefef;" colspan="6"|''Block unused''|-| 6C00h || 2 || N || W || SAR0 || "DMA" channel 0 address pointer|-| 6C02h || 1 || N || W || PPR0 || "DMA" channel 0 pause prescaler|-| 6C03h || 1 || || || || (unused)|-| 6C04h || 2 || N || W || SAR1 || "DMA" channel 1 address pointer|-| 6C06h || 1 || N || W || PPR1 || "DMA" channel 1 pause prescaler|-| 6C07h || 1 || || || || (unused)|-| 6C08h || 2 || N || W || SAR2 || "DMA" channel 2 address pointer|-| 6C0Ah || 1 || N || W || PPR2 || "DMA" channel 2 pause prescaler|-| 6C0Bh || 4 || || || || (unused)|-| 6C0Fh || 1 || Y || R/W || DCSR || "DMA" control/status register|-|style="background:#efefef;" colspan="6"|''Block unused''|} POR column indicates whether a register has power-on reset. A "N" indicates that the contents of a register are undefined at power-onfor details.
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