Changes
/* DMA channels and interrupt control */
The official documentation is not clear about the bits in the DCSR register (&6c0f), I found the following are correct:
{| class="wikitable"|-| Bit 7 || Raster Int|-| Bit 6 || DMA Channel 0 Interrupt|-| Bit 5 || DMA Channel 1 Interrupt|-| Bit 4 || DMA Channel 2 Interrupt|-| Bit 3 || not used|-| Bit 2 || DMA Channel 2 Enable|-| Bit 1 || DMA Channel 1 Enable|-| Bit 0 || DMA Channel 0 Enable|}
Each DMA opcode is two bytes, and is always fetched from an even address. The top 4-bits of the opcode fetched in the DMA cycle are used to specify the function to perform by the DMA.
I found the following rule:
If (opcode & 0x07 == 0) then write data to register else perform function defined by bits.
