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CRTC

238 bytes removed, 6 July
/* HSYNC and VSYNC */
== HSYNC and VSYNC ==
 
Bit0 of port B of the PPI is directly connected to the VSYNC pin of the CRTC.
The HSYNC width value is interpreted differently between CRTCs. On CRTCs 0/1, if 0 is programmed no HSYNC is generated. On CRTCs 2/3/4, if 0 is programmed this gives a HSYNC width of 16.
The HSYNC and VSYNC signals from the CRTC are passed to the [[Gate Array]] for further modification. See its wiki page.
 
Even if the number of lines of VSYNC is set to 1 in R3, the Gate Array (or ASIC) will output black for 26 lines, including 4 lines of C-VSYNC to the monitor. This is also true if the duration of the CRTC VSYNC is reduced to 2 µseconds.
 
Bit0 of port B of the PPI is directly connected to the VSYNC pin of the CRTC.
=== Ghost VSYNC ===
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