CRTCs 1/2 have a fixed VSYNC width value of 16. VSYNC width can be configured with Register 3 on CRTCs 0/3/4. If 0 is programmed this gives 16 lines of VSYNC.
The bit On CRTCs 0 /3/4, even if the number of lines of VSYNC is set to 1 in R3, the Gate Array will perform a full VSYNC of 26 lines. This is also true if the duration of the VSYNC produced by the CRTC is reduced to 2 µseconds. The bit0 of port B of the PPI changes to 1 as soon as immediately replicates the VSYNC signal that is produced by the CRTC.
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