Changes
ASIC
,/* Vectored Interrupt */
The register IVR (at address 6805h) supplies the top 5 bits of the vector provided to the CPU. It is undefined at reset except that bit0 will be set to 1. Therefore, before placing the CPU in vectored interrupt mode, always set up the IVR so that the top 5 bits are defined.
Bits2..1 of the IVR register are unused.
Interrupts are prioritized in a fixed sequence. The raster interrupt has the highest priority, followed by DMA channels 2 down to 0 respectively.
==== Interrupt Vector used on Z80 IM2 mode ====
{|{{Prettytable|width: 700px; font-size: 2em;}}
|''Interrupt Vector''||''Signal source''||''Value''
|-
|A15..A8||Z80||Register I
|-
|A7..A3||ASIC||IVR register bits7..3
|-
|A2..A1||ASIC||00 = DMA chan 2, 01 = DMA chan 1, 10 = DMA chan 0, 11 = DMA raster
|-
|A0||ASIC||Always 0
|}
<br>
