Changes

Additionally, on Amstrad Plus, we have multiple sources of interrupts as each DMA sound channel can trigger an interrupt. And the ASIC provides an  <br> == Vectored Interrupt == In this mode, interrupts are prioritized in a fixed sequence. The raster interrupt vector has the highest priority, followed by DMA channels 2 down to 0 respectively. The register (IVR(at address 6805h) for vectorized supplies the top 5 bits of the vector. It is undefined at reset except that bit0 will be set to 1. Software should therefore always set up the IVR before placing the CPU in vectored interrupt so that the top 5 bits are defined. Bit0 of the IVR controls whether DMA channel interruptsare automatically cleared.