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ASIC

144 bytes added, 5 July
/* DMA commands */
* The STOP instruction will leave the source address register pointing to the next instruction, so that the instruction stream can be continued after CPU intervention.
* The argument field (N) of the REPEAT instruction is actually the number of times the loop is taken. The block of code between REPEAT and LOOP instructions is therefore executed N+1 times.
* A DMA control and status register (DCSR) controls which channels are currently enabled, and also tells the CPU which channel is interrupting.
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