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ASIC

52 bytes removed, 5 July
== Split Screen ==
The 8-bit register SPLT (at address 6801h) specifies the scan line where the screen split occurs. Setting this register to 0 (the default value after at power-on resetup) will disable the split screen feature.
The 16-bit register SSA (high byte at address 6802h and low byte at address 6803h) defines the starting address in memory for displaying the lower part of the screen. These registers work similarly to R12/R13 in the CRTC. This configuration allows the lower part of the screen to be sourced from a different memory area and be scrolled independently. However, note that the soft scrolling register SSCR acts on the whole screen.
== Programmable Raster Interrupt ==
An The 8-bit memory-mapped register PRI (PRI) has been added within the ASIC at address 6800h, which is cleared ) specifies the scan line where the interrupt occurs. The interrupt will occur at the end of that scan line. Setting this register to 0 (the default value at power -up:* When PRI=0, ) will revert to the classic R52 raster interrupt system of the [[Gate Array]] functions as before* Otherwise, we have a programmable raster interrupt system instead: an interrupt will occur at the end of the scan line specified in PRI.
The PRI can be reprogrammed as required to produce multiple interrupts per frame.
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