Changes
/* Interrupt management */
*If interrupts are not authorized, then the R52 counter continues to increment and the interrupt remains armed (the Gate Array then maintains its INT signal). When interrupts are enabled (using the EI instruction) and '''after the instruction that follows EI''' (so not immediately after EI), bit5 of R52 is cleared and the interrupt takes place
Note: On Amstrad Plus, the Gate Array interrupt management system is not seriously beefed up. See the sole generator of interrupts. The 3 DMA sound channels are each able to trigger an interrupt. The [[ASIC also provides an interrupt vector register (IVR) for vectorized interrupts. And it offers a programmable raster interrupt register (PRI) that can be used instead of the normal raster interrupt mechanism]] wiki page.
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