Changes
/* Interrupt management */
*If interrupts are not authorized, then the R52 counter continues to increment and the interrupt remains armed (the Gate Array then maintains its INT signal). When interrupts are enabled (using the EI instruction) and '''after the instruction that follows EI''' (so not immediately after EI), bit5 of R52 is cleared and the interrupt takes place
Note: On Amstrad Plus, the Gate Array is not the sole generator of interrupts. Each of the 3 DMA sound channels are also able to trigger an interrupt. Also, the ASIC offers a programmable raster interrupt register (PRI) to trigger an interrupt at the end that can be used instead of any chosen scanlinenormal raster interrupt mechanism.
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