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/* The Screen RAM */OCR page 40
In theory, the Screen RAM could be any 16K byte area of memory starting at a multiple of 4000, but the 8000-BFFF block would overwrite workspace and RAM routines, while 0000-3FFF would overwrite the RST Area, so the choice narrows to 4000-7FFF or C000-FFFF, and it is usually more convenient to adopt the latter area, leaving the central half of RAM free for other purposes.
The Screen RAM is accessed by the Video Gate Array on a basis of addresses supplied by the CRT Controller, but the addresses are not used in a straightforward manner. The CRT Controller embodies two counters. One, output on RA0-RA4, is incrementedafter each line of the display has been scanned. When this count reaches the value set for the number of scan lines in the character height it is zeroed, and the second counter, output on MA0-MA13, is incremented. This counter is 1initialised to the Start Address set in the CRT Controller, which is 3000 when the C000-FFFF area is in use. These outputs are used as follows; * Address bits A14,A15 are driven from MA12,MA13. Since the MA counter works from a Start Address of 3000, both these bits are true. * Address bits A11-A13 are driven from RA0-RA3 * Address bits A11-A10 are driven from MA0-MA9 * Address bit A0 is driven from the CRT Controller clock. The scan line takes 40 microseconds to traverse the visible part of the display, and during each microsecond the Video Gate Array requires two bytes of screen data. These are transferred directly from RAM to the Video Gate Array, the processor being meanwhile held in Wait. The process is so timed that the GCRTC clock changes state between the two transfers. Once all the bytes have been read, the normal processor action is allowed to continue. The bytes are used in different ways in the three screen modes. In Mode 2, each byte defines one row of a character pattern matrix, each bit determining which of two colours should be given to a pixel, and eighty characters are displayed in each screen row. In Mode 1, two bytes are required to define each matrix row, two bits being used to give each pixel one of four colours. Successive pixels are defined by bits 3,7; 2,6; 1,5; and 0,4. This sequence is repeated in the second byte From each pair of bits, the Video Gate Array determines which palette entry should be used, and sets the colour accordingly. Since each matrix row requires two bytes, only forty characters can be displayed per screen row. In Mode 0, four bits are required to define one of sixteen colours for each pixel. This means that four bytes are required for each matrix row. The first pixel is defined by bits 1,5,3,7 of the first byte, the second by bits 0,4,2,6 and so on. Twenty characters can be displayed in each screen row. The way the CRT Controller counts are used complicates the
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