== Chapter 3 in the book [[Amstrad Whole Memory Guide]].: The Machine Pack ==
Chapter 3THE MACHINE PACKBroadly speaking, the Machine Pack is reponsible for the control of hardware peripherals, but it will be convenient to include the main initialisation processes under this heading, since they are largely concerned with peripheral setting-up.
Broadly speaking, Several of the Machine Pack is reponsible for routines depend on the control action ofhardware peripheralsother routines to set up data. To understand this data in full, but it will be convenient you need to include read 'The Ins and Outs of the maininitialisation processes under this headingAMSTRAD CPC464', since they are largelyconcerned with which gives full details of the peripheral setting-upcodes. Only the more essential codes will be defined here.
Several of the Machine Pack routines depend on the action ofother routines to set up data. To understand this data in full,you need to read 'The Ins and Outs of the AMSTRAD CPC464', whichgives full details of the peripheral codes. Only the moreessential codes will be defined here.=== Main Reset ===
Main ResetAt switch—on, or in response to instruction code &C7, location 0000 is entered. At switch-on, lower ROM is enabled, but the ROM routines are later copied to the corresponding RAM locations in this area, so the enable state of the lower ROM is then unimportant. However, the first action of the reset routine is to output &89 to the Video Gate array on I/0 address 7FXX, and this enables lower ROM, disables upper ROM, and also sets up Mode 1. There being no further room in the RST Area the routine jumps to 0580 to continue reset action.
At switch—onInterrupt is disabled, or in response to instruction code and &C7, location 0000 82 isenteredoutput to F7XX. At switch-on, lower ROM is enabled, but This sets the ROM routines arelater copied PPI (Parallel Peripheral Interface) to the corresponding RAM locations in this areaoutput on ports A and C, so theenable state of the lower ROM is then unimportantinput on port B. HoweverZero outputs to F4XX and F6XX clear ports A and C, the firstaction while an output of the reset routine is to output &89 7F to EFXX initialises the Video Gate arrayon I/0 address 7FXXprinter port. Bit 7 is low, and this enables lower ROM, disables upper ROM,and also sets up Mode 1. There being no further room in the RST Areathe routine jumps to 0580 to continue reset actionother bits are high.
Interrupt is disabled, and &82 is output to F7XX. This sets thePPI (Parallel Peripheral Interface) to output on ports A and C,input on port B. Zero outputs to F4XX and F6XX clear ports A andC, while an output of &7F to EFXX initialises the printer port.Bit 7 is low, the other bits are high. The CRT Controller is then set up. There are two alternative sets ofvalues for this, one for 50 Hz frame scan and the other for 60 Hz. Theset to be used is determined by reading port B, bit 4. If this bit istrue, 50 Hz values are used, while the 60 Hz values are used if thebit is false, this being determined by the presence of Link 4 on themain printed circuit board.
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