- Register 27 (PRIORITY CONTROL): Mask is &FF
* VRAM read/write via registers, 0,1,2 and 3,4,5 and port 0 use *logical* addresses and not physical addresses. Writing in one mode, and then reading back in another can yield data in a different order because the addresses are translated from logical to physical based on the mode. * Register index is masked with &3f. e.g. This means reading "register 64" is the same as reading register 0.
=== Palette ===
