Changes
/* Technical */
* After reset (including software reset using the control port), all registers are reset to 0. In addition the selected register (port 4) is set to 0 and read and write increment are not inhibited.
* If using software reset and the reset is held, then reading from ports or writing to the vram data port will cause the CPC to hang. I believe it's asserting /WAIT, but I can't confirm.
* Some registers have additional bits which are not documented. The mask describes which bits are read/write and which are unchanged.
* In terms of physical addresses, if you consider physical address 0-&3ffff to be VRAM0 and physical address &40000-&7ffff to be VRAM1, then in P1 mode, the physical address equals logical address and in bitmap modes, every even address maps to &0-&3ffff (ever even is VRAM0) and every odd address maps to &40000-&7ffff (VRAM 1). This is described in the PDF.
* When reading 2bpp and 4bpp data with the POINT command in bitmap modes the pixel is moved into the topmost bits. The value of the remaining bits is unknown at this time.
e.g.
* setting a partial vram write address is ok. e.g. set r0,r1,r2 to &80000, now set r1 to 1. Write will go to 000001. Now set r2 to 2. Write will go to 000201. Now set R3 to 3. Write will go to 030201. There doesn't appear to be a write buffer.
* v9990 seems to have a 1 byte read buffer. Setting a partial address and the reading vram will return the data from the previous full address set for the first read, but further reads returns correct values. This is only true of r3 and r4. e.g. set r3,r4,r5 to &80000. Now set r3 to 1. First read will come from &000000, second and subsequent reads now come from &000001. Now set r4 to 2. First read comes from &000001, second and subsequent reads come from &000201. Now set r5 to 3. First read comes from &030201, subsequent reads come from &030201.
[[Category:Hardware]]
