Changes
/* Technical */
OUT (C),A
* Bits 1,0 of R14 define a ternary counter. If you counter is set this to 3 then reads will return 0 and writes are ignored. If auto increment is enabled, it will increment as normal. When ternary counter is 2 or 3, then palette index will increment and ternary counter will go to 0.
e.g.
LD BC,&FF61
IN A,(C) ;; read returns last value written to port
e.g.
LD BC,&FF61
LD A,&FF
OUT (C),A ;; palette index will be 1, and ternary counter is 0.
* If a command transfers data, and it requests data to be written to the command data port, then you can't use a read of this port to clear the data request. It must be a write. Similarly, if a command requests data to be read then you can use a write to clear the data request.
* If you read from a write-only register you will see data-bus value because the V9990 doesn't assert data on the bus.
* After reset (including software reset using the control port), all registers are reset to 0. In addition the selected register (port 4) is set to 0 and read and write increment are not inhibited.
* If using software reset and the reset is held, then reading from ports will cause the CPC to hang. I believe it's asserting /WAIT, but I can't confirm.
* Some registers have additional bits which are not documented. The mask describes which bits are read/write and which are unchanged.
