Changes
/* Instruction timing : talk about r005.8.16c20 */
ralferro explains also that stretching instruction timing depends of memory used or not by instruction. I know that Amstrad schematics does not use the MEM_WR wire. So it could be hard to deduce if they added 1 or more WAIT_n for certain instructions. But I'm more about 1 WAIT_n inserted at maximum each time (it's more easy to hard implements), and the modulo 4 synchro, let's see results of my current experiment (comparing time instruction of Z80 and plustest.dsk testbench, deducing diff table of "slowing down instructions") wip.
==== Instruction timing : talk about r005.8.16c29 ====
This version does implements correctly a theorical WAIT_n generator : I used a script comparing Z80 doc timings to plustest.dsk testbench result on real CPC, I deduce that inserting each time 2 WAIT_n does the stuff. I also revisited the edges of WAIT_n generator, to insert WAIT_n at 2T.
I also removed the edge detection of IO_ACK on gatearray, replacing it by state detection of IO_ACK, resulting cpctest's testbench back : this test of HSYNC width is now successfull.
{| class="wikitable"
|-
! Hex !! Inst !! CPC timing !! r005.8.16c29
|-
| 32 || LD (nn),A || 4|| 3
|-
| 3A || LD A,(nn) || 4 || 3
|-
| C0 || RET NZ || 2/4 || 2/3
|-
| C4 || CALL NZ,nn || 3/5 || 3/4
|-
| C5 || PUSH BC || 4 || 3
|-
| C7 || RST 0H || 4 || 3
|-
| C8 || RET Z || 4/2 || 3/2
|-
| CC || CALL Z,nn || 5/3 || 4/3
|-
| CD || CALL nn || 5 || 4
|-
| CF || RST 8H || 4 || 3
|-
| D0 || RET NC || 2/4 || 2/3
|-
| D4 || CALL NC,nn || 3/5 || 3/4
|-
| D5 || PUSH DE || 4 || 3
|-
| D7 || RST 10H || 4 || 3
|-
| D8 || RET C || 4/2 || 3/2
|-
| DC || CALL C,nn || 5/3 || 4/3
|-
| DF || RST 18H || 4 || 3
|-
| E0 || RET PO || 2/4 || 2/3
|-
| E3 || EX (SP),HL || 6 || 5
|-
| E4 || CALL PO,nn || 3/5 || 3/4
|-
| E5 || PUSH HL || 4 || 3
|-
| E7 || RST 20H || 4 || 3
|-
| E8 || RET PE || 4/2 || 3/2
|-
| EC || CALL PE,nn || 5/3 || 4/3
|-
| EF || RST 28H || 4 || 3
|-
| F0 || RET P || 2/4 || 2/3
|-
| F4 || CALL P,nn || 3/5 || 3/4
|-
| F5 || PUSH AF || 4 || 3
|-
| F7 || RST 30H || 4 || 3
|-
| F8 || RET M || 4/2 || 3/2
|-
| FC || CALL M,nn || 5/3 || 4/3
|-
| FF || RST 38H || 4 || 3
|}
=== Test of a real Zilog 80 ===
