Changes

As said above, There were various revisions of the multiface watches Multiface 2: * There was a version which was visible to software all the bus for writes time. * One version had a "invisibility" switch on the front in addition to I/O ports, the stop and memorizes reset buttons. When switched in one direction the written values (required since most multiface was invisible to software and in the other it was visible.Is there a dump of the Gate Array ROM from this version? * Last revision had an automatic "invisibility" switch internally controlled by the hardware itself. After reset the multiface was visible, but when the stop button was pressed and CRTC ports are write-only)then control was returned to the running program it would be invisible and would remain invisible until the computer was reset. Reading  If the memorized values multiface 2 is probably done via these Ivisible you can enable/O portsdisable the ROM and RAM in the CPU's address space:* #FEE8 Multiface II - Enable Multiface II To make the ROM/and RAM visible to the CPU: * Enable lower rom using port 7fxx as normal ld bc,&7f89 out (Wc),c* #FEEA Multiface II - Disable Multiface II Then activate the ROM/and RAM : ld bc,&fee8 out (Wc),cWriting any value to these I/O ports enables/disables * To deactivate the 8K ROM and 8K RAM in the Multiface. When enabled: ld bc, the ROM/RAM are mapped to following addresses&feea out (c),c Testing shows the port is decoded as: ‭11111110111010exx means any value for this bite is 0 for enable and 1 for disable. * 0000h-1FFFh Multiface ROM is visible in the range &0000-&1fff. (including [[NMI]] vector at 0066h). Writing to the ROM doesn't write through to CPC's RAM.* 2000hRAM is visible in the range &2000-3FFFh Multiface &3fff. Writing to the RAMdoesn't write through to CPC's RAM.with the The internal ROM/RAM at 0000h-3FFFh in the CPC being disabled. You can write to *ANY* byte of the RAM including those which store the hardware state. The Multiface 2 listens to Gate-Array and PAL writes (port 7fxx), CRTC writes (bcxx and bdxx) and 8255 Control port writes (f7xx). Gate-Array and PAL are decoded as ‭01111111xxxxxxxx, CRTC as ‭10111100xxxxxxxx and ‭10111101xxxxxxxx and 8255 writes as ‭11110111xxxxxxxx.When the I/O write is detected, then specific locations in the MF2 RAM are updated immediately. Gate-Array pen index write (7fxx with bit 7=0 and bit 6=0): 3fcfGate-Array border colour write (7fxx with bit 7=0 and bit 6=1): 3fdfGate-Array pen colour write (7fxx with bit 7=0 and bit 6=1): 3f90-3f9f (pens 0 to 15)Gate-Array mode write (7fxx with bit 7=1 and bit 6=0): 3fefPAL write (7fxx with bit 7=1 and bit 6=1): 3fffCRTC register select write (bcxx): 3cffCRTC register data (bdxx): 1db0-1dbf (only registers 0-15, others are ignored)8255 Control port write (f7xx): 37ff The value that is stored is the value written. The automatic switch version of the multiface works by monitoring opcode reads from 0064 or 0065. There is a single call to 0065 (which has a RET) before the multiface 2 returns control back to the running program. It's not possible to activate the multiface ram and rom and call it directly, the multiface 2 must be in a specific state to accept the call and make itself invisible.