Changes
Created page with 'The Z80-STI is a 40pin MK3801 chip from Mostek. STI stands for Serial Timer Interrupt controller. The timers can be used as baudrate generators. The interrupt feature is designed…'
The Z80-STI is a 40pin MK3801 chip from Mostek. STI stands for Serial Timer Interrupt controller. The timers can be used as baudrate generators. The interrupt feature is designed for Z80 CPUs (but isn't used in the CPC).
== Usage in CPC ==
Used by the Schneider RS232 Interface:
Port 0h..0Fh mapped to F8E0h..F8EFh (default; can be jumpered to other ports)
Timer Clock source is 4MHz from expansion port
Timer C,D outputs (pin 3,4) are wired to Rx,Tx clock inputs (pin 39,36):
Timer C = Rx baudrate, Timer D = Tx baudrate, Timer A/B = Not used
General Purpose pins I0..I7 are wired as so:
I0=DTR, I1=RTS, I2=CTS, I3=DSR, I4=CHRDET, I5-I7=NC
INT output is not connected to CPC
Also used by Tim Riemann's DIY schematic:
Exactly same as Schneider RS232 Interface, except that,
Port F8E0h..F8EFh are fixed (no jumpers for other port addresses)
I4=NC (no CHRDET support)
== Register Summary ==
The Z80-STI chip has 16 directly addressable registers (eg. F8E0h..F8EFh):
Port 00h - Indirect Data Register
Port 01h - General Purpose I/O Data Register (0=Low, 1=High)
Port 02h - Interrupt Pending Register B (write 0=clear, 1=unchanged)
Port 03h - Interrupt Pending Register A (write 0=clear, 1=unchanged)
Port 04h - Interrupt in-Service Register B
Port 05h - Interrupt in-Service Register A
Port 06h - Interrupt Mask Register B (0=masked, 1=unmasked)
Port 07h - Interrupt Mask Register A (0=masked, 1=unmasked)
Port 08h - Indirect Index and Interrupt Vector Register
Port 09h - Timers A and B Control Register
Port 0Ah - Timer B Data Register
Port 0Bh - Timer A Data Register
Port 0Ch - USART Control Register
Port 0Dh - Receiver Status Register
Port 0Eh - Transmitter Status Register
Port 0Fh - USART Data Register
Plus 8 indirectly addressable registers (accessed via Port 00h and 08h):
Indirect 0 - Sync Character Register
Indirect 1 - Timer D Data Register
Indirect 2 - Timer C Data Register
Indirect 3 - Active Edge Register (0=Falling, 1=Rising)
Indirect 4 - Interrupt Enable Register B
Indirect 5 - Interrupt Enable Register A
Indirect 6 - Data Direction Register (0=Input, 1=Output)
Indirect 7 - Timers C and D Control Register
== Details ==
'''Port 00h - Indirect Data Register'''
0-7 Data to/from currectly selected Indirect Register
Note: The Indirected Register is selected via LSBs of Port 08h.
----
'''Port 08h - Indirect Index and Interrupt Vector Register'''
0-2 Indirect Register Index (for being accessed via Port 00h)
3 In-Service Register Enable
4 General Purpose Bit (acts as 1bit general purpose RAM)
5-7 Interrupt Vector Bits5-7
Note: Interrupt Vector Bit0 is fixed (zero), Bit1-4 depend on interrupt type, Bit5-7 are set by this register, Bit8-15 are defined in the CPU's "I" register. The interrupt types are, with 0Fh=Highest and 00h=Lowest priority,
0Fh General Purpose Interrupt 7 (I7-pin)
0Eh General Purpose Interrupt 6 (I6-pin)
0Dh Timer A
0Ch Receive Buffer Full
0Bh Receive Error
0Ah Transmit Buffer Empty
09h Transmit Error
08h Timer B
07h General Purpose Interrupt 5 (I5-pin)
06h General Purpose Interrupt 4 (I4-pin) or TA, Timer A Input (PW-Event)
05h Timer C
04h Timer D
03h General Purpose Interrupt 3 (I3-pin) or TB, Timer B Input (PW-Event)
02h General Purpose Interrupt 2 (I2-pin)
01h General Purpose Interrupt 1 (I1-pin) or DMA (TR)TX (Transmit)
00h General Purpose Interrupt 0 (I0-pin) or DMA (RR)REC (Receive)
----
'''Port 0Ch - USART Control Register'''
0 DMA Control Enable
1 Parity Type (0=Odd, 1=Even)
2 Parity Enable (0=Off, 1=On)
3-4 Stop Bits (0=Sync Mode, 1..3 = 1bit, 1.5bit, 2bit)
5-6 Character Size (0..3 = 8bit, 7bit, 6bit, 5bit)
7 Prescaler (0..1 = /1, /16)
Note: Sync Mode works without Start/Stop-bits. The "1.5bit" stop bit setting can be used in /16 prescaler mode.
----
'''Port 0Dh - Receiver Status Register'''
0 Receiver Enable
1 Sync Strip Enable
2 Match/Character in progress
3 Found/Search on Break Detect
4 Frame Error
5 Parity Error
6 Overrun Error
7 Buffer Full
----
'''Port 0Eh - Transmitter Status Register'''
0 Transmitter Enable
1-2 Serial Output State (0=Hi-Z, 1=Low, 2=High, 3=Loopback)
3 Break
4 End of Transmission
5 Auto Turnaround
6 Underrun Error
7 Buffer Empty
Note: "Loopback" connects transmitter output to receiver input (for selftest purposes or so).
----
'''Port 0Fh - USART Data Register'''
0-7 Rx/Tx Character
----
'''Indirect 0 - Sync Character Register'''
0-7 Sync Character
----
'''Port 0Ah - Timer B Data Register'''<br>
'''Port 0Bh - Timer A Data Register'''<br>
'''Indirect 1 - Timer D Data Register'''<br>
'''Indirect 2 - Timer C Data Register'''
0-7 Timer Value
----
'''Port 09h - Timers A and B Control Register'''
0-2 Timer B Prescaler (0..7 = Stop, /4, /10, /16, /50, /64, /100, /200)
3 Timer B Mode (0=Delay Mode, 1=Pulse Width Mode)
4-6 Timer A Prescaler (0..7 = Stop, /4, /10, /16, /50, /64, /100, /200)
7 Timer A Mode (0=Delay Mode, 1=Pulse Width Mode)
Note: The combination "Stop + Pulse Width" (4bit value 1000b) acts as "Event Count Mode".
----
'''Indirect 7 - Timers C and D Control Register'''
0-2 Timer D Prescaler (0..7 = Stop, /4, /10, /16, /50, /64, /100, /200)
3 Timer B Reset
4-6 Timer C Prescaler (0..7 = Stop, /4, /10, /16, /50, /64, /100, /200)
7 Timer A Reset
----
'''Port 02h - Interrupt Pending Register B (write 0=clear, 1=unchanged)'''<br>
'''Port 04h - Interrupt in-Service Register B'''<br>
'''Port 06h - Interrupt Mask Register B (0=masked, 1=unmasked)'''<br>
'''Indirect 4 - Interrupt Enable Register B'''
0 General Purpose Interrupt 0
1 General Purpose Interrupt 1
2 General Purpose Interrupt 2
3 General Purpose Interrupt 3
4 Timer D
5 Timer C
6 General Purpose Interrupt 4
7 General Purpose Interrupt 5
----
'''Port 03h - Interrupt Pending Register A (write 0=clear, 1=unchanged)'''<br>
'''Port 05h - Interrupt in-Service Register A'''<br>
'''Port 07h - Interrupt Mask Register A (0=masked, 1=unmasked)'''<br>
'''Indirect 5 - Interrupt Enable Register A'''
0 Timer B
1 Transmit Error
2 Transmit Buffer Empty
3 Receive Error
4 Receive Buffer Full
5 Timer A
6 General Purpose Interrupt 6
7 General Purpose Interrupt 7
----
'''Port 01h - General Purpose I/O Data Register (0=Low, 1=High)'''<br>
'''Indirect 3 - Active Edge Register (0=Falling, 1=Rising)'''<br>
'''Indirect 6 - Data Direction Register (0=Input, 1=Output)'''
0-7 Setting for I0..I7 pins
Alternate meanings are I0=RR, I1=TR (DMA related), I3=TB, I4=TA (Timer inputs).
== Datasheet ==
Note: Details on the MK3801 chip are found in the "MOSTEK 1982/1983 Microelectronic Data Book". The MK68901 seems to be a newer/similar chip (but neither port addresses nor pinouts are backwards compatible).
== Usage in CPC ==
Used by the Schneider RS232 Interface:
Port 0h..0Fh mapped to F8E0h..F8EFh (default; can be jumpered to other ports)
Timer Clock source is 4MHz from expansion port
Timer C,D outputs (pin 3,4) are wired to Rx,Tx clock inputs (pin 39,36):
Timer C = Rx baudrate, Timer D = Tx baudrate, Timer A/B = Not used
General Purpose pins I0..I7 are wired as so:
I0=DTR, I1=RTS, I2=CTS, I3=DSR, I4=CHRDET, I5-I7=NC
INT output is not connected to CPC
Also used by Tim Riemann's DIY schematic:
Exactly same as Schneider RS232 Interface, except that,
Port F8E0h..F8EFh are fixed (no jumpers for other port addresses)
I4=NC (no CHRDET support)
== Register Summary ==
The Z80-STI chip has 16 directly addressable registers (eg. F8E0h..F8EFh):
Port 00h - Indirect Data Register
Port 01h - General Purpose I/O Data Register (0=Low, 1=High)
Port 02h - Interrupt Pending Register B (write 0=clear, 1=unchanged)
Port 03h - Interrupt Pending Register A (write 0=clear, 1=unchanged)
Port 04h - Interrupt in-Service Register B
Port 05h - Interrupt in-Service Register A
Port 06h - Interrupt Mask Register B (0=masked, 1=unmasked)
Port 07h - Interrupt Mask Register A (0=masked, 1=unmasked)
Port 08h - Indirect Index and Interrupt Vector Register
Port 09h - Timers A and B Control Register
Port 0Ah - Timer B Data Register
Port 0Bh - Timer A Data Register
Port 0Ch - USART Control Register
Port 0Dh - Receiver Status Register
Port 0Eh - Transmitter Status Register
Port 0Fh - USART Data Register
Plus 8 indirectly addressable registers (accessed via Port 00h and 08h):
Indirect 0 - Sync Character Register
Indirect 1 - Timer D Data Register
Indirect 2 - Timer C Data Register
Indirect 3 - Active Edge Register (0=Falling, 1=Rising)
Indirect 4 - Interrupt Enable Register B
Indirect 5 - Interrupt Enable Register A
Indirect 6 - Data Direction Register (0=Input, 1=Output)
Indirect 7 - Timers C and D Control Register
== Details ==
'''Port 00h - Indirect Data Register'''
0-7 Data to/from currectly selected Indirect Register
Note: The Indirected Register is selected via LSBs of Port 08h.
----
'''Port 08h - Indirect Index and Interrupt Vector Register'''
0-2 Indirect Register Index (for being accessed via Port 00h)
3 In-Service Register Enable
4 General Purpose Bit (acts as 1bit general purpose RAM)
5-7 Interrupt Vector Bits5-7
Note: Interrupt Vector Bit0 is fixed (zero), Bit1-4 depend on interrupt type, Bit5-7 are set by this register, Bit8-15 are defined in the CPU's "I" register. The interrupt types are, with 0Fh=Highest and 00h=Lowest priority,
0Fh General Purpose Interrupt 7 (I7-pin)
0Eh General Purpose Interrupt 6 (I6-pin)
0Dh Timer A
0Ch Receive Buffer Full
0Bh Receive Error
0Ah Transmit Buffer Empty
09h Transmit Error
08h Timer B
07h General Purpose Interrupt 5 (I5-pin)
06h General Purpose Interrupt 4 (I4-pin) or TA, Timer A Input (PW-Event)
05h Timer C
04h Timer D
03h General Purpose Interrupt 3 (I3-pin) or TB, Timer B Input (PW-Event)
02h General Purpose Interrupt 2 (I2-pin)
01h General Purpose Interrupt 1 (I1-pin) or DMA (TR)TX (Transmit)
00h General Purpose Interrupt 0 (I0-pin) or DMA (RR)REC (Receive)
----
'''Port 0Ch - USART Control Register'''
0 DMA Control Enable
1 Parity Type (0=Odd, 1=Even)
2 Parity Enable (0=Off, 1=On)
3-4 Stop Bits (0=Sync Mode, 1..3 = 1bit, 1.5bit, 2bit)
5-6 Character Size (0..3 = 8bit, 7bit, 6bit, 5bit)
7 Prescaler (0..1 = /1, /16)
Note: Sync Mode works without Start/Stop-bits. The "1.5bit" stop bit setting can be used in /16 prescaler mode.
----
'''Port 0Dh - Receiver Status Register'''
0 Receiver Enable
1 Sync Strip Enable
2 Match/Character in progress
3 Found/Search on Break Detect
4 Frame Error
5 Parity Error
6 Overrun Error
7 Buffer Full
----
'''Port 0Eh - Transmitter Status Register'''
0 Transmitter Enable
1-2 Serial Output State (0=Hi-Z, 1=Low, 2=High, 3=Loopback)
3 Break
4 End of Transmission
5 Auto Turnaround
6 Underrun Error
7 Buffer Empty
Note: "Loopback" connects transmitter output to receiver input (for selftest purposes or so).
----
'''Port 0Fh - USART Data Register'''
0-7 Rx/Tx Character
----
'''Indirect 0 - Sync Character Register'''
0-7 Sync Character
----
'''Port 0Ah - Timer B Data Register'''<br>
'''Port 0Bh - Timer A Data Register'''<br>
'''Indirect 1 - Timer D Data Register'''<br>
'''Indirect 2 - Timer C Data Register'''
0-7 Timer Value
----
'''Port 09h - Timers A and B Control Register'''
0-2 Timer B Prescaler (0..7 = Stop, /4, /10, /16, /50, /64, /100, /200)
3 Timer B Mode (0=Delay Mode, 1=Pulse Width Mode)
4-6 Timer A Prescaler (0..7 = Stop, /4, /10, /16, /50, /64, /100, /200)
7 Timer A Mode (0=Delay Mode, 1=Pulse Width Mode)
Note: The combination "Stop + Pulse Width" (4bit value 1000b) acts as "Event Count Mode".
----
'''Indirect 7 - Timers C and D Control Register'''
0-2 Timer D Prescaler (0..7 = Stop, /4, /10, /16, /50, /64, /100, /200)
3 Timer B Reset
4-6 Timer C Prescaler (0..7 = Stop, /4, /10, /16, /50, /64, /100, /200)
7 Timer A Reset
----
'''Port 02h - Interrupt Pending Register B (write 0=clear, 1=unchanged)'''<br>
'''Port 04h - Interrupt in-Service Register B'''<br>
'''Port 06h - Interrupt Mask Register B (0=masked, 1=unmasked)'''<br>
'''Indirect 4 - Interrupt Enable Register B'''
0 General Purpose Interrupt 0
1 General Purpose Interrupt 1
2 General Purpose Interrupt 2
3 General Purpose Interrupt 3
4 Timer D
5 Timer C
6 General Purpose Interrupt 4
7 General Purpose Interrupt 5
----
'''Port 03h - Interrupt Pending Register A (write 0=clear, 1=unchanged)'''<br>
'''Port 05h - Interrupt in-Service Register A'''<br>
'''Port 07h - Interrupt Mask Register A (0=masked, 1=unmasked)'''<br>
'''Indirect 5 - Interrupt Enable Register A'''
0 Timer B
1 Transmit Error
2 Transmit Buffer Empty
3 Receive Error
4 Receive Buffer Full
5 Timer A
6 General Purpose Interrupt 6
7 General Purpose Interrupt 7
----
'''Port 01h - General Purpose I/O Data Register (0=Low, 1=High)'''<br>
'''Indirect 3 - Active Edge Register (0=Falling, 1=Rising)'''<br>
'''Indirect 6 - Data Direction Register (0=Input, 1=Output)'''
0-7 Setting for I0..I7 pins
Alternate meanings are I0=RR, I1=TR (DMA related), I3=TB, I4=TA (Timer inputs).
== Datasheet ==
Note: Details on the MK3801 chip are found in the "MOSTEK 1982/1983 Microelectronic Data Book". The MK68901 seems to be a newer/similar chip (but neither port addresses nor pinouts are backwards compatible).
