Changes
* [[CIO Registers (Summary)]]
* [[CIO Registers (Detailed)]]
== CPU Interface ==
=== Data Ports ===
* Data Port A (same as CIO Register 0Dh) (R/W)
* Data Port B (same as CIO Register 0Eh) (R/W)
* Data Port C (same as CIO Register 0Fh) (R/W)
These three ports allow to access Data Port A-C directly, using a single IN/OUT opcode (alternately, they can be also accessed in two-opcode form, via the Control Port, with Register Number = 0Dh..0Fh).
=== Control Port ===
* Control Port (R/W)
This port gives access to all CIO registers. First write the desired register number, then read/write the corresponding register's data:
First Access:
6bit CIO Register Number (00h..2Fh) (Write Only)
Second Access:
8bit Data read/written to/from selected register (Read/Write)
The First/Second Access Flipflop is TOGGLED on any write, and CLEARED on any read (ie. a dummy read can be used to force it to First Access state).
A special case is the reset feature: After setting register[00h].Bit0=1, the chip gets stuck in the 2nd Access phase, until one writes Bit0=0 in a 3rd access.
== Port A/B/C Features ==
Port A (PA0-PA7) - 8bit I/O Port
Port B (PB0-PB7) - 8bit I/O Port, or Counter/Timer 1 and 2
Port C (PC0-PC3) - 4bit I/O Port, Counter/Timer 3, or handshake /WAIT REQ
== Port B/C - Counter/Timer External Access Modes ==
Function______________C/T1____C/T2____C/T3___
Counter/Timer Output PB 4 PB 0 PC 0
Counter Input PB 5 PB 1 PC 1
Trigger Input PB 6 PB 2 PC 2
Gate Input PB 7 PB 3 PC 3
== Port C Bit I/O and Special Modes ==
Port A/B Configuration_______PC3__________PC2__________PC1__________PC0_____
Ports A and B: Bit Ports Bit I/O Bit I/O Bit I/O Bit I/O
Port A: Input or Output Port RFD or /DAV /ACKIN REQ/WAIT Bit I/O
(Interlocked, Strobed or
Pulsed Handshake) (*)
Port B: Input or Output Port REQ/WAIT Bit I/O RFD or /DAV /ACKIN
(Interlocked, Strobed or
Pulsed Handshake) (*)
Port A or B: Input Port RFD (Out) /DAV (In) REQ/WAIT DAC (Out)
(3-Wire Handshake)
Port A or B: Output Port /DAV (Out) DAC (In) REQ/WAIT RFD (In)
(3-Wire Handshake)
Port A or B: Bidirectional RFD or /DAV /ACKIN REQ/WAIT IN/OUT
Port (Interlocked or
Strobed Handshake)
(*) Both Ports A and B can be specified input or output with Interlocked, Strobed, or Pulsed Handshake at the same time if neither uses REOUEST/WAIT.
Notes: All pins marked "REQ/WAIT" can be REQUEST/WAIT, or Bit I/O. /DAV means Data Available, RFD means Ready for Data, DAC means whatever?.
