Changes
/* 8255 PIO Port B Input */
|}
The CIO chip is a counter Counter and I/O chip. In the KC compact system it is used to generate interrupts, access to the parallel printer port, and possibly video control.
When A12 of the I/O address is "0", the CIO is selected. Bit A9 and A8 of the I/O address select the registers of the CIO,
to avoid conflict with other peripherals the Z8536 CIO should be access using:
{|{{Prettytable|width: 700px; font-size: 2em;}}
(note: A8 is passed through an inverter and this describes the order of the registers in the table compared to the order of the registers in the CIO datasheet)
On start-up, the KC compact programs the z8536 CIO to the following state:
* Port A: I/O mode: all bits are set to output, and bit 7 is inverted when writing. (bit 7 is /strobe signal to printer)
What this means:
* The Z8536 CIO Port C counter is updated when HSYNC changes state* The Z8536 CIO Port C counter is reset when VSYV changes state
With the default settings, the Z8536 CIO will count 26 HSYNC transitions (52 lines of the display covered in this time) and generate a interrupt. At VSYNC the counter is reset so that the interrupts are synchronised.
I do not know the exact function of the counter's of Port B. I have looked at the schematics, and it appears to control the video hardware. Maybe the KC compact has a programmable pixel clock, if it does, then the base resolution can be changed.
* interrupt can be cleared by writing to bit 4 of Mode/ROM register at 0x07fxx (counter is *not* reset at this time)
* interrupt system fully programmable: can count HSYNCS, or count internal Z8536 CIO clocks!
Therefore, the KC compact interrupt system is more powerful than the CPC!
When the KC compact is reset, the /TEST signal on the expansion port is checked.
