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Gate Array<br>Introduction<br>The gate array is a specially designed chip exclusively for use in the Amstrad CPC and was designed by Amstrad plc.
== Introduction ==
The gate array is a specially designed chip exclusively for use in the Amstrad CPC and was designed by Amstrad plc.
In the CPC+ system, the functions of the Gate-Array are integrated into a single ASIC. When the ASIC is "locked", the extra features are not available and the ASIC operates the same as the Gate-Array in the CPC allowing programs written for the CPC to work on the Plus without modification. The ASIC must be "un-locked" to access the new features.
The Gate Array is described here, as it is in a standard CPC.
What does it do?<br>The Gate Array is responsible for the display (colour palette, resolution, horizontal and vertical sync), interrupt generation and memory arrangement.
== Controlling the Gate Array == The gate array is controlled by I/O. The gate array is selected when bit 15 of the I/O port address is set to "0" and bit 14 of the I/O port address is set to "1". The values of the other bits are ignored. However, to avoid conflict with other devices in the system, these bits should be set to "1". The recommended I/O port address is &7Fxx.
The function to be performed is selected by writing data to the Gate-Array, bit 7 and 6 of the data define the function selected (see table below). It is not possible to read from the Gate-Array.
Bit 7 Bit 6 Function <br> 0 0 Select pen <br>0 1 Select colour for selected pen <br>1 1 Select screen mode, rom configuration and interrupt control <br>1 1 Ram Memory Management (note 1)
This function is not available in the Gate-Array, but is performed by a device at the same I/O port address location. In the CPC464,CPC664 and KC compact, this function is performed in a memory-expansion (e.g. Dk'Tronics 64K Ram Expansion), if this expansion is not present then the function is not available. In the CPC6128, this function is performed by a PAL located on the main PCB, or a memory-expansion. In the 464+ and 6128+ this function is performed by the ASIC or a memory expansion. Please read the document on Ram Management for more information. <br>Pen selection<br>When bit 7 and bit 6 are set to "0", the remaining bits determine which pen is to have its colour changed. When bit 4 is set to "0", bits 3 to 0 define which pen is to be selected. When bit 4 is set to "1", the value contained in bits 3-0 is ignored and the border is selected.
LD BC,&7F00 ;Gate Array port<br>LD A,%00000000+0 ;Pen number (and Gate Array function)<br>OUT (C),A ;Send pen number<br>LD A,%01000000+11 ;Pen colour (and Gate Array function)<br>OUT (C),A ;Send it<br>RET
