Changes
CRTC
,* to adapt the software so that it will run with the detected 6845
* In most cases, the type of the detected 6845 is reported
<br>
The CRTC is not connected to the CPU's RD and WR pins, so it cannot detect the bus's I/O direction. Therefore, executing an IN instruction to the select or write functions causes the CRTC to write the unpredictable data provided by the high-impedance bus to its registers.
<br>
=== Z80 I/O access timings ===
The clock provided to the CRTC by the ASIC/Pre-ASIC is phase-shifted compared to the one provided by the Gate Array.
{| class="wikitable"
|+
! Instructions !! Duration !! I/O CRTCs 0/1/2 !! I/O CRTCs 3/4
|-
| OUT (C),r8 || 4 µsec || '''3rd µsec''' || 4th µsec
|-
| OUT (C),0 || 4 µsec || '''3rd µsec''' || 4th µsec
|-
| OUT (n),A || 3 µsec || 3rd µsec || 3rd µsec
|-
| OUTI || 5 µsec || 5th µsec || 5th µsec
|-
| OUTD || 5 µsec || 5th µsec || 5th µsec
|-
| IN r8,(C) || 4 µsec || 4th µsec || 4th µsec
|-
| INI || 5 µsec || '''4th µsec''' || '''4th µsec'''
|-
| IND || 5 µsec || '''4th µsec''' || '''4th µsec'''
|-
| IN A,(n) || 3 µsec || 3rd µsec || 3rd µsec
|}
<br>
