Changes

Jump to: navigation, search

CRTC

No change in size, Yesterday at 02:13
/* PPI VSYNC */
The VSYNC pin of the CRTC is directly connected to bit0 of port B of the PPI. There is no delay involved.
On Amstrad CPC (not Plus!), it is also possible to reverse the direction of PPI port B to output a ("fake) " VSYNC signal directly from the PPI to the Gate Array.
As an exception, the Ghost VSYNC of CRTC 2 overpowers the Fake VSYNC.
8,290
edits