Changes
/* Register RMR2 (ASIC & Advanced ROM mapping) */
== Interrupt management ==
Interrupts on the CPC are created by the Gate Array based on settings from the CRTC. The Gate Array has an internal counter (R52(the R is for Raster) that counts from 0 to 51, incrementing after each HSYNC signal.
R52 will return to 0 and the Gate Array will send an interrupt request on any of these conditions:
The function to be performed is selected by writing data to the Gate Array, the first bits of the data define the function selected (see table below). It is not possible to read from the Gate Array.
{|{{Prettytable|width: 700px; font-size: 2em;}}|-class="wikitable"
!colspan=4| 8bit command
!rowspan=2| Machine
==== Summary ====
{|{{Prettytable|width: 700px; font-size: 2em;}}class="wikitable"|-| ''!Bit'' || ''!Value'' || ''!Function''
|-
| 7 || 0 || rowspan="2" | Gate Array PENR register
<br>
{|{{Prettytable|width: 700px; font-size: 2em;}}class="wikitable"|-| ''!Bit'' || ''!Value'' || ''!Function''
|-
| 7 || 0 || rowspan="2" | Gate Array PENR register
==== Summary ====
{|{{Prettytable|width: 700px; font-size: 2em;}}class="wikitable"|-| ''!Bit'' || ''!Value'' || ''!Function''
|-
| 7 || 0 || rowspan="2" | Gate Array INKR register
The function of bits 1 and 0 is to define the screen mode. The settings for bits 1 and 0 and the corresponding screen mode are given in the table below.
{|{{Prettytable|width: 700px; font-size: 2em;}}class="wikitable"|-| ''!Bit 1'' || ''!Bit 0'' || ''!Screen mode''
|-
| 0 || 0 || Mode 0, 160x200 resolution, 16 colours
==== Summary ====
{|{{Prettytable|width: 700px; font-size: 2em;}}class="wikitable"|-| ''!Bit'' || ''!Value'' || ''!Function''
|-
| 7 || 1 || rowspan="2" | Gate Array RMR register
This register exists only in Plus or GX4000, and is only accessible when the ASIC is unlocked.
{|{{Prettytable|width: 700px; font-size: 2em;}}class="wikitable"|-| ''!Bit'' || ''!Value'' || ''!Function''
|-
| 7 || 1 || rowspan="3" | Gate Array RMR2 register
