Changes

== I/O Ports ==

|-

|#7FXX||%01xxxxxx xxxxxxxx||[[Gate Array]]||-||Write

== Memory Mapped I/O Ports ==

|-

|#4000-7FFF||%01xxxxxx xxxxxxxx||ASIC - CPC+/GX4000 registers|| Read || Write

The [[ASIC]] I/O page is defined as follows:

|-

| 4000h || 100h || N || R/W || || Sprite 0 image data

| 4F00h || 100h || N || R/W || || Sprite 15 image data

|-

|-

| 6000h || 2 || N || R/W || X0 || Sprite 0 X position

| 607Dh || 3 || || || || (unused)

|-

|-

| 6400h || 2 || N || R/W || || Colour palette, pen 0

| 643Eh || 2 || N || R/W || || Colour palette, sprite colour 15

|-

|-

| 6800h || 1 || Y || W || PRI || Programmable raster interrupt scan line

| 6805h || 1 || N || W || IVR || Interrupt Vector (Bit 0 set to 1 on reset)

|-

|-

| 6808h || 1 || || R || ADC0 || Analogue input channel 0

| 680Fh || 1 || || R || ADC7 || Analogue input channel 7

|-

|-

| 6C00h || 2 || N || W || SAR0 || "DMA" channel 0 address pointer

|-

| 6C0Fh || 1 || Y || R/W || DCSR || "DMA" control/status register

|}

POR column indicates whether a register has power on reset. A "N" indicates that the contents of a register are undefined at power on.

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