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Disclaimers

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CRTC

6 July 2024

Phi2x
→‎HSYNC and VSYNC
15:20
+176
Phi2x
→‎HSYNC and VSYNC
14:42
-238
Phi2x
→‎Immediate Border
13:13
Phi2x
→‎DISPTMG (aka Display Enable)
13:13
+26
Phi2x
→‎HSYNC and VSYNC
13:03
+253
Phi2x
→‎HSYNC and VSYNC
12:36
+138
Phi2x
→‎HSYNC and VSYNC
11:44
Phi2x
→‎HSYNC and VSYNC
11:43
-8
Phi2x
→‎HSYNC and VSYNC
11:42
+4
Phi2x
→‎HSYNC and VSYNC
11:42
+8
Phi2x
→‎HSYNC and VSYNC
11:34
-1
Phi2x
→‎HSYNC and VSYNC
11:32
+10
Phi2x
→‎HSYNC and VSYNC
11:30
-16
Phi2x
→‎HSYNC and VSYNC
11:16
-8
Phi2x
→‎HSYNC and VSYNC
11:11
+1
Phi2x
→‎HSYNC and VSYNC
10:46
-20
Phi2x
→‎HSYNC and VSYNC
10:45
+2
Phi2x
→‎HSYNC and VSYNC
10:45
-4
Phi2x
→‎HSYNC and VSYNC
10:43
-8
Phi2x
→‎HSYNC and VSYNC
10:38
-16
Phi2x
→‎HSYNC and VSYNC
10:34
+15
Phi2x
→‎HSYNC and VSYNC
10:34
+31
Phi2x
→‎HSYNC and VSYNC
10:33
-2
Phi2x
→‎HSYNC and VSYNC
10:32
+2
Phi2x
→‎HSYNC and VSYNC
10:32
+225
Phi2x
→‎CRTC counter differences
10:00
-24
Phi2x
→‎Overscan bits
09:52
-1
Phi2x
→‎Overscan bits
09:51
+12
Phi2x
→‎VCC (C4) overflow
09:33
-12
Phi2x
→‎VTAC (C5/C9) overflow
09:15
-12
Phi2x
→‎Internal Counters
07:54
+12
Phi2x
→‎MA buffering
07:44
+21
Phi2x
→‎CRTC counter differences
07:41
+7
Phi2x
→‎MA reload
07:38
+13
Phi2x
→‎MA reload
07:37
+1
Phi2x
→‎CRTC counter differences
07:30
+21
Phi2x
→‎MA reload
07:27
-2
Phi2x
→‎MA reload
07:26
+34
Phi2x
→‎CRTC counter differences
07:24
+1
Phi2x
→‎CRTC counter differences
07:23
+1
Phi2x
→‎CRTC counter differences
07:22
Phi2x
→‎Overscan bits
06:26
-55
Phi2x
→‎Addressing
06:24
+1,924
Phi2x
→‎CRTC registers
06:24
-1,924
Phi2x
→‎CRTC registers
06:22
+23
Phi2x
→‎MA reload
05:40
Phi2x
→‎MA reload
05:38
-28
Phi2x
→‎CRTC counter differences
05:34
+3
Phi2x
→‎CRTC register differences
05:24
Phi2x
→‎CRTC register differences
05:23
+22

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