Difference between revisions of "SYMBiFACE II:Rewriteable roms"
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The re-writeable ROMs are stored on a static RAM. The static RAM is powered by a CR2032 battery to remember it's contents when the symbiface 2 is powered down. | The re-writeable ROMs are stored on a static RAM. The static RAM is powered by a CR2032 battery to remember it's contents when the symbiface 2 is powered down. | ||
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| + | J2 on the Symbiface 2 controls visibility of roms 8-31 to the CPC. J2 when connected stops them being visible, when disconnected roms 8-31 are visible. | ||
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| + | There are 8 switches which control visibility of roms 0-7 to the CPC. | ||
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| + | When J2 is connected and all switches are off then no roms are visible. This now allows you to program the ROMs safely. | ||
== Mechanisms == | == Mechanisms == | ||
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{|{{Prettytable|width: 700px; font-size: 2em;}} | {|{{Prettytable|width: 700px; font-size: 2em;}} | ||
| − | |'''INP &FD17''' || show the current ROM (selected by #df00) between #4000 and #7fff. Now it can be read and | + | |'''INP &FD17''' || show the current ROM (selected by #df00) between #4000 and #7fff. Now it can be read and written. All roms on the Symbiface 2 can be accessed this way regardless of J2 or dipswitches state. You also do not need to enable the upper rom using port #7fxx. |
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| − | |'''OUT &FD17''' || disable the | + | |'''OUT &FD17''' || disable the previously mentioned ROM write mode. Any value can be written. |
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| − | |'''OUT &FD11''' || disable all SYMBiFACE II Roms. | + | |'''OUT &FD11''' || disable all SYMBiFACE II Roms. The roms will not be visible to the CPC, you will only see CPC's inbuilt ones or ROMs from other rom-boards. |
|- | |- | ||
| − | |'''INP &FD11''' || enable the SYMBiFACE II roms. | + | |'''INP &FD11''' || enable the SYMBiFACE II roms. Symbiface 2 roms will be visible if enabled through J2 or switches. |
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Revision as of 05:34, 31 January 2016
This article decribes, how to map the rewriteable ROMs of the SYMBiFACE II card into the ram area so that you can change its content.
The re-writeable ROMs are stored on a static RAM. The static RAM is powered by a CR2032 battery to remember it's contents when the symbiface 2 is powered down.
J2 on the Symbiface 2 controls visibility of roms 8-31 to the CPC. J2 when connected stops them being visible, when disconnected roms 8-31 are visible.
There are 8 switches which control visibility of roms 0-7 to the CPC.
When J2 is connected and all switches are off then no roms are visible. This now allows you to program the ROMs safely.
Mechanisms
Please note, that the following commands ignore all values. So it doesn't matter, what you "out". When you "inp" you won't get any meaningful numbers.
| INP &FD17 | show the current ROM (selected by #df00) between #4000 and #7fff. Now it can be read and written. All roms on the Symbiface 2 can be accessed this way regardless of J2 or dipswitches state. You also do not need to enable the upper rom using port #7fxx. |
| OUT &FD17 | disable the previously mentioned ROM write mode. Any value can be written. |
| OUT &FD11 | disable all SYMBiFACE II Roms. The roms will not be visible to the CPC, you will only see CPC's inbuilt ones or ROMs from other rom-boards. |
| INP &FD11 | enable the SYMBiFACE II roms. Symbiface 2 roms will be visible if enabled through J2 or switches. |
