* CLK is known to be 4MHz, and SIN is known to be updated on falling edge of CLK, as seen on [[Media:ACID-SIN.jpg|this picture]].
* Judging from the ACID chip, /CCLR is checked on falling edge of CLK. However, juding from [[Media:ACID-CCLR.png| this picture]], /CCLR is ''changing'' on falling edge of CLK. If this is true (the picture resolution isn't perfect), then it's unclear how the ACID can interprete /CCLR in a stable way while it's changing. Possibly, it can't do that at all (ie. it might act unstable, and the CPC+ might need to retry sending /CCLR several times).
** '''WANTED:''' A picture showing CLK and /CCLR without ACID connected (at better resolution) would help!
** A picture showing CLK and /CCLR with ACID connected is [[Media:ACID Init by Grim.png|found here]].
* The /CE timing is still unknown, too. The ACID might check A0-A7 on raising or falling edge of /CE. Or, on raising or falling edge of CLK while /CE being LOW. Or at whatever other time.
** '''WANTED:''' A picture showing CLK and /CE would help!** '''WANTED:''' Best also showing one or more of the A0-A7 signals.
== Pinout ==