Difference between revisions of "Aleste 520EX"

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== PPI 8255 ==
 
== PPI 8255 ==
  
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{|{{Prettytable|width: 700px; font-size: 2em;}}
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Works similar to the [[8255]] in the CPC (see there for details). Differences are listed below.
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|''I/O address''||''A9''||''A8''||''Description''||''Read/Write status''||''Used Direction''||''Used for''
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|&F4xx||0||0||Port A Data||Read/Write||In/Out||[[PSG]] (Sound/Keyboard/Joystick/Printer, Baudrate/Future Timer, and RTC)
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|&F5xx||0||1||Port B Data||Read/Write||In||Vsync/Jumpers/PrinterBusy/CasIn/Exp
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|&F6xx||1||0||Port C Data||Read/Write||Out||KeybRow/CasOut/PSG
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|&F7xx||1||1||Control||Write Only||Out||Control
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=== PPI Port A ===
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=== PPI Port A (Port F4xxh) ===
  
 
{|{{Prettytable|width: 700px; font-size: 2em;}}
 
{|{{Prettytable|width: 700px; font-size: 2em;}}
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|''Bit''||''Description''||''Usage''
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|''Bit''||''Description''||''Usage in CPC''||''Usage in Aleste''
 
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|-
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|7-0||PSG.DATA||[[PSG]] Databus (Sound/Keyboard/Joystick/Printer, Baudrate/Future Timer, and RTC)
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|7-0||PSG.DATA||[[PSG]] Databus (Sound/Keyboard/Joystick)||[[PSG]] Databus (Sound/Keyboard/Joystick/Printer, Baudrate/Future Timer, and RTC)
 
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|}
  
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=== PPI Port B ===
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=== PPI Port B (Port F5xxh) ===
  
 
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{|{{Prettytable|width: 700px; font-size: 2em;}}
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=== PPI Port C ===
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=== PPI Port C (Port F6xxh) ===
  
 
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=== PPI Control ===
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=== PPI Control (Port F7xxh) ===
  
 
This register has two different functions depending on bit7 of the data written to this register.
 
This register has two different functions depending on bit7 of the data written to this register.
 +
 
See the normal CPCs [[8255]] description for details.
 
See the normal CPCs [[8255]] description for details.
  

Revision as of 14:54, 5 February 2010

Aleste 520EX - a CPC clone housed in a case with MSX keyboard

The Aleste 520EX is a clone of the Amstrad CPC 6128 developed 1993 Patisonic in Omsk (Siberia). The Aleste is rare, according to Patisonic themselves, they "produced several dozens of the model, some of them was in 'kit' form".

Additionally to the standard CPC6128 features, it includes a number of extra features: 64-color palette, double color depth (eg. 16 color at high 320x200 resolution), battery-backed Real Time Clock chip, 512Kbyte RAM (of which 192K can be accessed as on 64K CPC with 128K dk'tronics memory expansion), 8bit printer port, expanded keyboard matrix with 10 additional keys, two software controlled LEDs, extended Expansion Port (with additional pins for DMA support).

The computer works with Amstrad CP/M and MSXDOS as well (note: MSXDOS is a CP/M clone, which uses a FAT filesystem, as used on MSX and MS-DOS computers, instead of the normal CP/M filesystem).

Amstrad Mode

Differences:

- Interrupts can't be manually cleared. This was possible on the CPC by writing to the Gate Array with data bit 7 set 1, bit 6 set to 0 and bit 4 set to 1. In the Aleste this bit is controls an LED.

- Decoding of it's equivalent of the Gate-Array is based on A15 only.

- The Aleste uses a patched CPC6128 Operating System ROM. It is patched to use the Aleste's 8-bit printer port and has a different startup message.

Special Mode

At this mode computer have different memory manager. The manager seems same like MSX mapper and could swicth ON any 16KB page of whole memroy at the any of 16KB page of CPU memory.

The mode have different color coding system. It has the color lookup table (CLUT) or another name pallette. That is dual port memory one prot for coversion pixel's color number to RGB levels. But second for CPU acccess. There is 2 bits for each channel at the pallette present, then it lets to have 64 colors.

The mode have two additional modes with 32KB of video memory. Pixel encoding the same as at Amstrad mode but each line has twice more bytes (and pixels). Two 16KB pages transfer to output, one buffer for odd and second even lines of screen.

The computer have also mc146818 compatible RTC and a 8251 compatible serial. A serial mouse can be used.

The 8253 timer is used to generate transmit and receive clock for serial. In addition the CURSOR output of the CRTC is connected as a trigger which is then connected to the colour hardware. So the CRTC cursor can be used to switch colours by the hardware.

Aleste ROM is 64KB:

  • page 0 is modified Amstrad CPC6128 OS ROM
  • page 1 is Amstrad BASIC
  • page 2 is AMSDOS (Amstrad DOS)
  • page 3 is Boot Rom, BIOS Setup, MSXDOS boot loader

The BIOS SETUP lets control over: date and time, boot drive, RAM disk, screen mode and style, printer, serial port, and mouse.

At the boot time computer loads BIOS and MSXBDOS (BIOS for Disc BIOS) from a bood disc. After that COMMAND.COM (MSXDOS). Computer can bott from RAM disc as well. Computer go to AMSTRAD mode when "Shift" is pressed while reset.

Magic Sound Expansion Board

Additional sound board MagicSound is a four channel DMA playback. Supports 8 bit per sample, 6 bits of volume per channel, and 16bit samplerate timer per channel. Computer uses the board for playing STM (Scream Tracker) files.

VDP Emulator

It is not clear exactly what this is.

It seems to describe a collection of software functions (BIOS or library) which aids with converting MSX or MSX2 games to the Aleste.

Certainly the games that have been converted to Aleste are patched, and it seems they do not access any special I/O ports.

It doesn't appear to be an emulator as such, and it seems the Aleste should be modified to run at 8Mhz to run the games at sufficient speed.


Computer have "GameBios" with is emulator of VDP9938. it was sufficiently - to replace the first several kilos-byte of game and MSX2 game worked. Certainly, video processor MSX is by apparatus sharpened for the games, but they worked sufficiently rapidly to 8MGts of game on "alesta" in order in them to play. Game "FireBird" typical "vertical scroller" worked very well.

Foton Expansion Board

Another additional board FOTON is a "Light Processor". The board have D54 interface and Aleste with special FX application controls over club's light.

Pictures

  • Pictures from http://aleste520.narod.ru

  • PCB and Keyboard

  • PCB top (component side)

  • PCB bottom (solder side)

  • PCB illustrated

The above photos are showing a more or less fully assembled Aleste (the LEDs are missing, and, more important, there is no connection for an internal or external power supply attached to the mainboard - unless the owner used the Expansion Port connector to inject power supply voltages).

  • Pictures from http://www.zonadepruebas.com

  • PCB and Keyboard

  • PCB only

  • Rear-connectors

  • Bottom

This version has 7pin+7pin sockets for printer (normal would be 5pin+7pin, though the extra pins are most probably left unused).

Schematics (edited, with corresponding western part numbers)

  • Schematic 1/4

  • Schematic 2/4

  • Schematic 3/4

  • Schematic 4/4

  • Component Map

For reference, the original unedited schematics are here: Sheet 1, Sheet 2, Sheet 3, Sheet 4, and Component Map

Documents

I/O Map (Overview)

I/O Decoded as Port Read Write
#7CXX %0xxxxx00 xxxxxxxx Aleste RAM Mapper page 0 Read Write
#7DXX %0xxxxx01 xxxxxxxx Aleste RAM Mapper page 1 Read Write
#7EXX %0xxxxx10 xxxxxxxx Aleste RAM Mapper page 2 Read Write
#7FXX %0xxxxx11 xxxxxxxx Aleste RAM Mapper page 3 Read Write
#7FXX %0xxxxxxx xxxxxxxx Customized Gate Array (Aleste Multiport)] - Write
#BCXX %x0xxxx00 xxxxxxxx 6845 CRTC Index - Write
#BDXX %x0xxxx01 xxxxxxxx 6845 CRTC Data Out - Write
#BEXX %x0xxxx10 xxxxxxxx 6845 CRTC Status (as far as supported) Read -
#BFXX %x0xxxx11 xxxxxxxx 6845 CRTC Data In (as far as supported) Read -
#DFXX %xx0xxxxx xxxxxxxx Upper ROM Bank Number (bank 3 = Aleste Bootmenu) - Write
#F4XX %xxxx0x00 xxxxxxxx 8255 PIO Port A (PSG/8253 Timer/Real-Time Clock data) Read Write
#F5XX %xxxx0x01 xxxxxxxx 8255 PIO Port B (Vsync,PrnBusy,Tape,etc.) Read -
#F6XX %xxxx0x10 xxxxxxxx 8255 PIO Port C (KeybRow, Real-Time-Clock control,,Tape,PSG Control) - Write
#F7XX %xxxx0x11 xxxxxxxx 8255 PIO Control-Register - Write
#FA7E %xxxxx0x0 0xxxxxxx Floppy Motor Control (for 765 FDC) - Write
#FABF %xxxxx0x0 1xxxxxxx Aleste EXTPORT - Write
#FB7E %xxxxx0x1 0xxxxxx0 765 FDC (internal) Status Register Read -
#FB7F %xxxxx0x1 0xxxxxx1 765 FDC (internal) Data Register Read Write

Aleste RAM Mapper

Four I/O ports control the mapper:

I/O Decoded as Page Memory region
#7CXX %0xxxxx00 xxxxxxxx page 0 &0000-&3fff
#7DXX %0xxxxx01 xxxxxxxx page 1 &4000-&7fff
#7EXX %0xxxxx10 xxxxxxxx page 2 &8000-&bfff
#7FXX %0xxxxx11 xxxxxxxx page 3 &c000-&ffff

The decoding of the I/O port for the mapper uses bit 15 of the I/O address in the same way as the Aleste "Gate Array".

Bit 9,8 define which page.

To avoid writing to the Aleste "Gate-Array" bits 7 and 6 of the data must be 1.

The remaining bits define the RAM block/configuration to use.

In CPC mode, writing to the mapper changes the RAM configuration for all pages, with the memory configuration being the same as a DK'Tronics compatible RAM.

In Aleste mapper mode, writing to the mapper changes the RAM for one page.

It is not know:

  • Must you write to #7Fxx in CPC mode to define RAM configuration or can you also use #7Cxx, #7Dxx, #7Exx for same effect
  • When you write CPC RAM configuration is it mirrored in all mapper registers?

Aleste 8bit Printer Port

Printer data-bits are connected to AY I/O port B (PSG register 15). Printer strobe is connected to 8255 port C bit 4. The strobe is negated by the hardware. Printer busy is connected to 8255 port B bit 6.

Aleste Gate Array (aka Patasonic's Multiport)

Aleste "Gate Array" is similar in functionality to the Gate-Array in the CPC/Plus.

bit 7 bit 6 Action
0 0 Gate Array Register 0 - Pen index write
0 1 Gate Array Register 1 - Pen ink write
1 0 Gate Array Register 2 - Mode, Rom enable, Leds
1 1 Gate Array Register 3 - Used by mapper

Gate Array Register 0

Pen index:

bit Action
7 0
6 0
5 not used
4 If set to 1, border is selected
3..0 Pen index

Gate Array Register 1

The number is converted by IC D62.

  • When MAPPER is set in EXTPORT, then the numbers effectively define a R,G,B colour with 2 bits per element, but the rom then changes the order of the bits before it gets to the hardware.
  • When MAPPER is not set, the number is equivalent to the CPC's Gate-Array colour value, but this is looked up in IC D62 and converted into a 2-bit per element R,G,B for the aleste video hardware.

Gate Array Register 2

bit Action
7 0
6 1
5 CAPS LED
4 RUS LED
3 Upper rom enable/disable
2 Lower rom enable/disable
1..0 Mode

bit 0,1 define the mode. The actual resolution is then dependant on bit 1 of EXTPORT. When HIGHTX is 0, CPC modes are chosen. When HIGHTX is 1, Aleste modes are chosen.

CPC modes:

bit 1 bit 0 Mode
0 0 160x200 (16 colours)
0 1 320x200 (4 colours)
1 0 640x200 (2 colours)
1 1 Don't know. On CPC this is 160x200 (4 colours)

Aleste modes:

bit 1 bit 0 Mode
0 0 Don't know
0 1 Don't know
1 0 Don't know
1 1 Seems to be 320x200 (16 colours)

Gate Array Register 3

In the CPC register 3 was not handled by the Gate-Array.

The 16L8 PAL IC was also mapped at the same I/O address as the Gate-Array and bit 7 and 6 of the data had to be 1 to avoid conflict with other Gate-Array registers.

In the Aleste register 3 is effectively Mapper select.

Writing to port #7Fxx with bit 7 and bit 6 of data set to 1 can be used to set page 3 RAM bank in Aleste mapper mode, or to define CPC RAM configuration in CPC mode.

Upper ROM Bank

The number is looked up in D62 and converted into another number which is the 16K page index in the Aleste's internal 64k ROM.

Ext Port

bit Action
7 not used
6 not used
5 if 0, then AY is accessed when read/write to 8255 port A, if 1 then real-time clock is accessed with read/write to 8255 port A. When real-time clock is selected, bits 3..0 of PPI port C are used to define real-time clock operation. DS bit 2, AS bit 1, R/W bit 0. So combinations are 2, write address, 4 write data, 5 read data.
4 Enable 8253 timer. Any I/O write then accesses 8253 with data comming from 8255 port A. Bit A0/A1 of I/O port defines 8253 register
3 force video to black
2 enable/disable MAPMOD (changes how colour is decoded and how mapper values are decoded),
1 Enables high resolution in X. Also changes some clock frequences. Controls decoding of video address.
0 Not fully understood yet. Controls decoding of video address

PPI 8255

Works similar to the 8255 in the CPC (see there for details). Differences are listed below.

PPI Port A (Port F4xxh)

Bit Description Usage in CPC Usage in Aleste
7-0 PSG.DATA PSG Databus (Sound/Keyboard/Joystick) PSG Databus (Sound/Keyboard/Joystick/Printer, Baudrate/Future Timer, and RTC)

PPI Port B (Port F5xxh)

Bit Description Usage in CPC Usage in Aleste
7 CAS.IN Cassette data input Same as on CPC
6 PRN.BUSY Parallel/Printer port ready signal, "1" = not ready, "0" = Ready Same as on CPC
5 /EXP Expansion Port /EXP pin Wired to GND (uh, BUT, Aleste Expansion Port DOES have an /EXP pin?)
4 LK4 Screen Refresh Rate ("1"=50Hz, "0"=60Hz) Same as in CPC
3 LK3 Manufacturer ID bit3 LK3 is shortcut to LK2, and wired to a pull-up resistor
2 LK2 Manufacturer ID bit2
1 LK1 Manufacturer ID bit1 /DISCINT (the /INT pin from FDC 765)
0 CRTC VSYNC Vertical Sync ("1"=VSYNC active, "0"=VSYNC inactive) Same as on CPC (though using emulated timings from VDKEY eprom)

PPI Port C (Port F6xxh)

Bit Description Usage in CPC Usage in Aleste
7 PSG BDIR PSG function selection Same as in CPC
6 PSG BC1
5 Cassette Write data Cassette Out (and Printer Bit7, see 8bit Printer Ports) Cassette Out
4 Cassette Motor Control Cassette Motor (0=Off, 1=On) Printer Strobe (0=High, 1=Low)
3 Keyboard line Select keyboard line to be scanned (0-15) Same as CPC, but, Aleste uses 0..10 (whilst CPC uses only 0..9)
2
1
0

PPI Control (Port F7xxh)

This register has two different functions depending on bit7 of the data written to this register.

See the normal CPCs 8255 description for details.

Keyboard

The Aleste uses a MSX keyboard, as seen by the characteristic five function keys. The mainboard contains some excessive TTL logic, assisted by the upper data bits of the VDKEY eprom, that translates the MSX matrix to a CPC matrix.

So, at I/O port level, the CPU "sees" a CPC matrix, not a MSX matrix. When running MSXDOS, this leads to the funny situation that MSXDOS must undo the hardware MSX-to-CPC translation by some software CPC-to-MSX translation.

The keyboard has some additional keys, which aren't on normal CPC keyboards:

  • F1/F6, F2/F7, F3/F8, F4/F9, F5/F10 - MSX-style function keys, mapped to keyboard row 10, bits 7,6,5,4,3.
  • HELP, INS, b - additional keys, mapped to keyboard row 10, bits 2,1,0.
  • R/L - Russian/Latin mode, mapped to keyboard row 9, bit6 (aka joystick Fire3).
  • RES - Reset button, goes to /RESET signal.
  • Four unknown keys - These keys (above the numeric keypad) may be unused, or having same function as other keys?

The Aleste has a JCUKEN keyboard, rather than a QWERTY keyboard.

  • Unknown if this done by hardware, or by patched CPC bios (?)
  • Normally, the key next to TAB should be Row8.Bit3 in the CPC matrix. And the BIOS should assign "Q" to it for english QWERTY keyboards, "A" for french "AZERTY" keyboards - or "J" for russian JCUKEN keyboards (though not sure if Patisonic has implemented it that way).
 _____ _____ _____ _____ _____                 _____ _____ _____   _____ _____
|F1/6 |F2/7 |F3/8 |F4/9 |F5/10|               |HELP |INS  | DEL | |N/A  | RES |
|_____|_____|_____|_____|_____|               |_____|_____|_____| |_____|_____|
 _____ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ _____   ___ ___ ___
| ESC | ; | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 0 | _ | b |  BS | |N/A|N/A|N/A|
|_____|___|___|___|___|___|___|___|___|___|___|___|___|___|_____| |___|___|___|
|  TAB  | J | C | U | K | E | N | G | { | } | Z | H | : | / |   | | F7| F8| F9|
|_______|___|___|___|___|___|___|___|___|___|___|___|___|___|   | |___|___|___|
|  CTRL  | F | Y | W | A | P | R | O | L | D | V | \ | . |RETURN| | F4| F5| F6|
|________|___|___|___|___|___|___|___|___|___|___|___|___|______| |___|___|___|
|CAPS| R/L | Q | | | S | M | I | T | X | B | @ | '  |   | U |   | | F1| F2| F3|
|____|_____|___|___|___|___|___|___|___|___|___|____| L |___| R | |___|___|___|
|  SHIFT | COPY|         SPACE              | SHIFT |   | D |   | | F0| F.|ENT|
|________|_____|____________________________|_______|___|___|___| |___|___|___|

Technical specs

  • CPU: Z80
  • Clock: 4Mhz (CPC mode derived from a 16Mhz crystal), 3.2Mhz (Aleste mode derived from a 13Mhz crystal)
  • Memory manager: Dk'Tronics compatible memory mapper (CPC mode), msx-mapper (Aleste mode)
  • Memory: 512КБ (up to 2МБ)
  • Audio: AY8910
  • Graphics:
    • 256x212:16 colors
    • 512x212:4 colors
    • 320x200:16 colirs
    • 640x200:4 colors
    • 640x400:4 colors interleaved
    • Palette 64 colors
    • Hardware scroll (standard CRTC hardware scroll)
  • Floppy disk 3.5"
  • Mouse
  • RTC (mc146818 compatible)
  • Expansion slot
    • 19 address lines
    • DMA to whole memory
    • External board MagicSound
      • 4 channels
      • 8 bits per channel
      • Stereo output
  • Touch screen (only prototype)
  • Light-Processor with D54

Software

  • MSXDOS
  • С compiler
  • GUI Debugger
  • GameBIOS with VDP emulator
  • Text editor PowerEdit
  • Text files converter TRC. Convert between MSX, Aleste, and DOS
  • Disk Fixer (ported)
  • Disk Edit (ported)
  • Image viewer
  • Player of S3M, STM files
  • Editor of S3M, STM files
  • Games ported from MSX2
    • VampireKiller
    • KingValery 2
    • FireBird
    • MetalGear

Aleste Chipset

Note: The part numbers printed on the chips may look like "KPxxx" (cyrillic) instead of "KRxxx" (latin).

Main Chipset

pcs russian    western  description    location
 1  Z80A CPU   Z80A     CPU            (D30=sheet2)
 1  UM6845     6845     CRTC           (D25=sheet2)
 1  AY-3-8910  AY3-8910 PSG, Dual I/O  (D18=sheet2) (with TWO I/O ports, unlike as in CPC)
 4  KR1802IR1  AM29705  RAM 2x16x4     (D60,D61=sheet2=palette, D62,D63=sheet4=keyboard)
 1  KR1810WG72 uPD765   FDC            (D70=sheet3)
 1  KR580WI53  8253     baudrate timer (D33=sheet4) (/CS=/CS53, A0,A1=A0,A1, D0-D7=AY0-AY7=PPIpa) (/WR only, no /RD) (CLK0,CLK1=WGPTCLK=16MHz/n, see sheet3)
 1  KR580WW51A 8251(A?) usart/mouse    (D34=sheet2) (A12=/CS, A8=C/D)
 1  KR580WW55A 8255     PPI            (D17=sheet2)
 1  KR512WI1   MC146818 RTC            (D19=sheet2)
 16 K565RU7K   HM50256  DRAM 256Kx1    (D1..D16=sheet3) (512Kbyte)
 1  K573RF4    27512    EPROM 64Kx8    (D31=sheet2) (BIOS/BASIC/BOOT/AMSDOS)
 2  K573RF2    2764     EPROM 2Kx8     (D62=COLDAT=sheet1, D65=VDKEY=sheet1)
 1  K155RE3    27S18    PROM 32x8 OC   (D69="Af"=sheet3=floppy) (dummy FP0..FP3, disk /GATE, to D72 count --> DW --> FDC)
 2  (KR)556RT4 27S20    PROM 256x4 OC  (D28="M"=MAP14..MAP17=sheet2, D67="R"=ROMEN/RAMEN etc.=sheet1)

Further Chips

pcs russian    western  description              location
 1  K170AP2    SN75150  rs232 dual line driver   (D86=sheet4)
 1  K555AP6    74LS245  8bit 3state tranceiver   (D89=sheet3)
 2  K555ID4    74LS155  2x2bit decoder/demult    (D54=sheet1, D74=sheet3)
 1  K555ID10   74LS145  bcd demultiplexer        (D80=sheet4)
 1  K555IE5    74LS93   4bit (1bit+3bit) counter (D72=sheet3)
 1  K555IE10   74LS161  4bit counter             (D37=sheet1)
 4  K555IR11A  74LS194  4bit shift register      (D39,D49=sheet1, D50,D51=sheet2)
 4  K555IR22   74LS373  8bit 3state latch        (D45,D46,D47,D48=sheet1) (RAM 16bit-to-8bit cpu/vram bus)
 2  K555IR23   74LS374  8bit 3state flipflop     (D58=sheet3, D84=sheet4)
 2  K555IR32   74LS170  4x4bit register file OC  (D87,D88=sheet2)
 6  K555KP2    74LS153  2x 4vstup. multiplexer   (D20,D21,D22,D23,D52,D53=sheet2)
 2  K555KP7    74LS151  8bit multiplexer         (D24=sheet2,D81=sheet4)
 1  K555KP11   74LS257  8-to-4 data selector     (D38=sheet1) (clock select)
 1  K555KP12   74LS253  2x 4vstup. multiplexer, TS "8-to-2 line 3-state noninverting data selector/multiplexer" (D26=sheet3)
 .. K555LA3    74LS00   Quad NAND gates          (various)
 .. K555LE1    74LS02   Quad NOR gates           (various)
 .. K555LI1    74LS08   Quad AND gates           (various)
 .. K555LL1    74LS32   Quad OR gates            (various)
 .. K555LN1    74LS04   Hex inverters            (various)
 1  K555LN2    74LS05   Hex inverters, OC        (D76=sheet3)
 5  K555TM2    74LS74   Dual flipflop            (D40,D77,D66,D57=sheet1, D71=sheet3)
 6  K555TM9    74LS174  6bit flipflop            (D32,D55,D56=sheet1, D59=sheet2, D68=sheet3, D79=sheet4)
 1  K561IE10   MC14520B dual up binary counter   (D63,D64=sheet1)

Weblinks

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