Changes

Jump to: navigation, search

VHDL

1 byte added, 14:35, 5 March 2017
All instructions are run at the same time/edge. Next values being computed from previous values. The time an output value takes to be affected by an input value is called "delta-time". Like in "This cannot run !, you forgotten that it takes 4 delta-time to cross this 4 components !!!". There is a difference between delta-time and number of clock edges, as certain components are using rising_edge and others falling_edge. delta-time is just about vocabulary speaking, it is the time between the action is launched and then takes effect outside. In order to understood this concept, better is to play using "testbench" programs, showing sequence diagrams.
You can also have local registered valuevalues, using affectation operator ":=", without delta-time (at once) :
output_wire_mem := input_wire xor 1;
output_wire_mem := output_wire_mem xor 1;
1,200
edits