Difference between revisions of "VHDL"

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VHDL (very high-level description language)
+
VHDL (very high-level hardware description language)
  
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This is an electronic language having electronic behaviour. You can implement what you want numerical electronic schematics (you can also draw then and translate then into VHDL)
+
This is an electronic language having electronic behaviour. You can implement what you want numerical electronic schematics (you can also draw them and translate then into VHDL)
  
−
Its syntax does look like ADA language. It differs from computer langage as its first instruction does generaly look like :
+
Its syntax does looks like and is derived from the Ada language family. It differs from computer langage as its first instruction does generaly look like :
 
  if rising_edge(clock) then
 
  if rising_edge(clock) then
 
   output_wire <= input_wire xor 1;
 
   output_wire <= input_wire xor 1;
 
  end if;
 
  end if;
  
−
All instruction are runs at the same time/edge. Next values being computed from previous values. The time an output value takes to be affected by an input value is called "delta-time". Like in "This cannot run !, you forgotten that it takes 4 delta-time to cross this 4 components !!!". There is a difference between delta-time and number of clock edges, as certain components are using rising_edge and others falling_edge. delta-time is just about vocabulary speaking, it is the time between the action is launched and then takes effect outside. In order to understood this concept, better is to play using "testbench" programs, showing sequence diagrams.
+
All instructions are run at the same time/edge. Next values being computed from previous values. The time an output value takes to be affected by an input value is called "delta-time". Like in "This cannot run !, you forgotten that it takes 4 delta-time to cross this 4 components !!!". There is a difference between delta-time and number of clock edges, as certain components are using rising_edge and others falling_edge. delta-time is just about vocabulary speaking, it is the time between the action is launched and then takes effect outside. In order to understood this concept, better is to play using "testbench" programs, showing sequence diagrams.
  
−
You can also have local registered value, using affectation operator ":=", without delta-time (at once) :
+
You can also have local registered values, using affectation operator ":=", without delta-time (at once) :
 
  output_wire_mem := input_wire xor 1;
 
  output_wire_mem := input_wire xor 1;
 
  output_wire_mem := output_wire_mem xor 1;
 
  output_wire_mem := output_wire_mem xor 1;
 
  output_wire <= output_wire_mem;
 
  output_wire <= output_wire_mem;
  
−
VHDL can be synthetised (compiled) into [[FPGA]] chip. Two families of [[FPGA]] chips exists : Xilinx (Diligent starter-kits are really fun and instructive) and Altera (cheaper). You cannot really compare them, units are not the same between them...
+
== Application ==
 +
VHDL can be synthetised (compiled) into IP (Instruction set Processor) chips like [[CPLD]] and [[FPGA]] chips, apart from generating a [[netlist]] for [[ASIC]] building.  
 +
 
 +
Two families of [[FPGA]] chips exists : Xilinx (Diligent starter-kits are really fun and instructive) and Altera (cheaper). You cannot really compare them, units are not the same between them...
 +
 
 +
[[CPLD]]s are faster and do not need to re-load their instructions at power-up, but do not offer the flexibility of FPGAs. An Intel 386 has been simulated on a CPLD (Complex Programmable Logic Device). Two common families are Atheros (now Intel) and Altera.
 +
 
 +
 
 +
== Characteristics ==
 
VHDL is more strict than Verilog, Verilog is more C language like. Verilog seems more used in America and VHDL in Europe. But you can plug their components together using drawn schematics.
 
VHDL is more strict than Verilog, Verilog is more C language like. Verilog seems more used in America and VHDL in Europe. But you can plug their components together using drawn schematics.
  
 +
In order to use the same language concepts in Hardware Description (HDL - Hardware Description Language) and Software development, SystemC was also developed and standardised. There are, however, boni in using VHDL and Ada as development languages from the same family.
 +
 +
Alas, VHDL to-date lacks exception handling, apart from the Assert-pragma.
 +
 +
=== Standardisation ===
 +
VHDL is standardised in IEEE Std 1076 and its substandards. Parts fo them are also part of IEC standard 61691 "Behavioural Languages":
 +
* IEEE Std 1076.1 VHDL Language Reference Manual = IEC 61691-1-1
 +
* IEEE Std 1076.2 VHDL Mathematical Packages = IEC 61691-3-2
 +
* IEEE Std 1076.3 VHDL Synthesis Packages = IEC 61691-3-3
 +
* IEEE Std 1076.4 VITAL ASIC = IEC 61691-5
 +
* IEEE Std 1076.5 VHDL Register Transfer Level Synthesis
 +
* IEEE Std 1076.6 VHDL Analog and Mixed-Signal Extensions = IEC 61691-6
 +
 +
IEC 61691 is a standard for Behavioural Languages (Hardware Design Languages):
 +
* IEC 61691-1-1 VHDL LRM = IEEE Std 1076.1
 +
* IEC 61691-2 VHDL Multilogic System for Model Interoperability
 +
* IEC 61691-3-2: Mathematical Operation in VHDL
 +
* IEC 61691-3-3: Synthesis in VHDL
 +
* IEC 61691-4 Verilog HDL
 +
* IEC 61691-5 VITAL ASIC = IEEE Std 1076.4
 +
* IEC 61691-6 VHDL Analog and Mixed-Signal Extensions = IEEE Std 1076.6
 +
* IEC 61691-7 SystemC LRM
 +
 +
=== Ada language family ===
 +
Ada (iterations Ada83, Ada95, Ada2005 and Ada2012) offers strict typing and is a higher-level language much like PL/I and [[PL/M]] (the HLL used for programming [[CP/M]]); requirements to strictly adhere to standards kept it from forking into countless libraries and frameworks like C and Java. Exception handling (alas, NOT yet implemented in VHDL) and the ASSERT pragma (standard since Ada2005, implemented into VHDL) offer safety constraints. It came out of a 'ricain Department of Defence (DoD) concourse as the winner in 1976 and is an open standard from the start.
 +
 +
Ada became notorious after the ARIANE-5 self-destructed on her maiden voyage; however, it was human failure on the part of a programmer. After it was proven that variable type constraints could not be exceeded by the ARIANE-4, constraint checks were switched off to make the code faster. ARIADNE-5 however, designed as a carrier platform for the cancelled HERMES space shuttle project, was considerably heavier and values DID overflow; however, the programmers re-used ARIADNE-4 code without switching constraint checks (which would have prevented the accident) back on.
 +
 +
The US En Route Air Traffic Control system however in 2009 was completed using Ada2005 under budget and ahead of schedule [http://www.iaeng.org/publication/IMECS2009/IMECS2009_pp1095-1099.pdf due to Ada05's engineering capabilities].
 +
 +
Detrimental to Ada's widespread use in the FLOSS (Free/Libre Open Source Software) community are its "evilness" as a DoD standard and its "differentness" as a Wirthean language (akin to educational PASCAL) for C/C++-programmers; however, [http://www.cs.uni.edu/~mccormic/4740/guide-c2ada.pdf these differences DO address common C/C++ design flaws, so it can be considered an "acquired taste"]. Strongly typed, it tends to display faults ("hidden" points of failure) more often into direct errors (the compiler stops) rather than to allow them to manifest themselves as failures (system stops working suddenly).
 +
 +
Apart from ARIANE rockets and Air Traffic Control systems, it is also used in airplanes, medical technology, the PANAVIA Tornado, the Eurofighter Typhoon, Eurocopter Tigre and NH-90 systems, and about any mission-critical system a simple reboot on failure is no option. Since Ada95, there are Object Oriented addition to Ada. A superset of Ada called SPARK that can be compiled in normal Ada compilers (the extra instructions are inside comments) is for highly verified code; AdaDoc in Ada2012 offers a JavaDoc-like Documentation generation system.
 +
 +
The [http://www.kuhmann.com/Cromemco/Cromemco%20CS250.htm Cromemco CR-250 Motorola 68000 S-100] machine was in widespread use as USAF Mission Support System (1986-1990), so a CP/M Ada83 compiler should be available.
 +
 +
* [http://www.makewithada.org/ Make with Ada programming competition]
 +
* [http://adahome.com/ AdaHome - Home of the Brave Ada Programmers]
 +
* [http://ada-europe.org Ada Europe]
 +
== Tools ==
 
IDE :
 
IDE :
 
* Xilinx webpack
 
* Xilinx webpack
Line 30: Line 78:
 
** [http://www.amedia-computer.com Amedia Computer] - fr
 
** [http://www.amedia-computer.com Amedia Computer] - fr
  
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Books :
+
== Books ==
 
* Conception de circuits en VHDL et VHDL-AMS / Principes et méthodologie / Collection POLYTECH / Cépaduès-éditions / D. HOUZET L. BARRANDON
 
* Conception de circuits en VHDL et VHDL-AMS / Principes et méthodologie / Collection POLYTECH / Cépaduès-éditions / D. HOUZET L. BARRANDON
 
* VHDL-AMS / Applications et enjeux industiels / Cours et exercices corrigés / 2e et 3e cycles écoles d'ingénieurs/ DUNOD / Yannick Hervé
 
* VHDL-AMS / Applications et enjeux industiels / Cours et exercices corrigés / 2e et 3e cycles écoles d'ingénieurs/ DUNOD / Yannick Hervé
 +
 +
VHDL-AMS is theorical, it is about using an analog version of VHDL not running in FPGA. But VHDL-AMS books does cover also VHDL (if an author of book does understand VHDL-AMS, sure he does understand VHDL perfectly.....)
 +
 +
[[Category:Hardware]]

Latest revision as of 05:50, 11 March 2018

VHDL (very high-level hardware description language)

This is an electronic language having electronic behaviour. You can implement what you want numerical electronic schematics (you can also draw them and translate then into VHDL)

Its syntax does looks like and is derived from the Ada language family. It differs from computer langage as its first instruction does generaly look like : 

if rising_edge(clock) then
 output_wire <= input_wire xor 1;
end if;

All instructions are run at the same time/edge. Next values being computed from previous values. The time an output value takes to be affected by an input value is called "delta-time". Like in "This cannot run !, you forgotten that it takes 4 delta-time to cross this 4 components !!!". There is a difference between delta-time and number of clock edges, as certain components are using rising_edge and others falling_edge. delta-time is just about vocabulary speaking, it is the time between the action is launched and then takes effect outside. In order to understood this concept, better is to play using "testbench" programs, showing sequence diagrams.

You can also have local registered values, using affectation operator ":=", without delta-time (at once) : 

output_wire_mem := input_wire xor 1;
output_wire_mem := output_wire_mem xor 1;
output_wire <= output_wire_mem;

Application

VHDL can be synthetised (compiled) into IP (Instruction set Processor) chips like CPLD and FPGA chips, apart from generating a netlist for ASIC building.

Two families of FPGA chips exists : Xilinx (Diligent starter-kits are really fun and instructive) and Altera (cheaper). You cannot really compare them, units are not the same between them...

CPLDs are faster and do not need to re-load their instructions at power-up, but do not offer the flexibility of FPGAs. An Intel 386 has been simulated on a CPLD (Complex Programmable Logic Device). Two common families are Atheros (now Intel) and Altera.


Characteristics

VHDL is more strict than Verilog, Verilog is more C language like. Verilog seems more used in America and VHDL in Europe. But you can plug their components together using drawn schematics.

In order to use the same language concepts in Hardware Description (HDL - Hardware Description Language) and Software development, SystemC was also developed and standardised. There are, however, boni in using VHDL and Ada as development languages from the same family.

Alas, VHDL to-date lacks exception handling, apart from the Assert-pragma.

Standardisation

VHDL is standardised in IEEE Std 1076 and its substandards. Parts fo them are also part of IEC standard 61691 "Behavioural Languages":

  • IEEE Std 1076.1 VHDL Language Reference Manual = IEC 61691-1-1
  • IEEE Std 1076.2 VHDL Mathematical Packages = IEC 61691-3-2
  • IEEE Std 1076.3 VHDL Synthesis Packages = IEC 61691-3-3
  • IEEE Std 1076.4 VITAL ASIC = IEC 61691-5
  • IEEE Std 1076.5 VHDL Register Transfer Level Synthesis
  • IEEE Std 1076.6 VHDL Analog and Mixed-Signal Extensions = IEC 61691-6

IEC 61691 is a standard for Behavioural Languages (Hardware Design Languages):

  • IEC 61691-1-1 VHDL LRM = IEEE Std 1076.1
  • IEC 61691-2 VHDL Multilogic System for Model Interoperability
  • IEC 61691-3-2: Mathematical Operation in VHDL
  • IEC 61691-3-3: Synthesis in VHDL
  • IEC 61691-4 Verilog HDL
  • IEC 61691-5 VITAL ASIC = IEEE Std 1076.4
  • IEC 61691-6 VHDL Analog and Mixed-Signal Extensions = IEEE Std 1076.6
  • IEC 61691-7 SystemC LRM

Ada language family

Ada (iterations Ada83, Ada95, Ada2005 and Ada2012) offers strict typing and is a higher-level language much like PL/I and PL/M (the HLL used for programming CP/M); requirements to strictly adhere to standards kept it from forking into countless libraries and frameworks like C and Java. Exception handling (alas, NOT yet implemented in VHDL) and the ASSERT pragma (standard since Ada2005, implemented into VHDL) offer safety constraints. It came out of a 'ricain Department of Defence (DoD) concourse as the winner in 1976 and is an open standard from the start.

Ada became notorious after the ARIANE-5 self-destructed on her maiden voyage; however, it was human failure on the part of a programmer. After it was proven that variable type constraints could not be exceeded by the ARIANE-4, constraint checks were switched off to make the code faster. ARIADNE-5 however, designed as a carrier platform for the cancelled HERMES space shuttle project, was considerably heavier and values DID overflow; however, the programmers re-used ARIADNE-4 code without switching constraint checks (which would have prevented the accident) back on.

The US En Route Air Traffic Control system however in 2009 was completed using Ada2005 under budget and ahead of schedule due to Ada05's engineering capabilities.

Detrimental to Ada's widespread use in the FLOSS (Free/Libre Open Source Software) community are its "evilness" as a DoD standard and its "differentness" as a Wirthean language (akin to educational PASCAL) for C/C++-programmers; however, these differences DO address common C/C++ design flaws, so it can be considered an "acquired taste". Strongly typed, it tends to display faults ("hidden" points of failure) more often into direct errors (the compiler stops) rather than to allow them to manifest themselves as failures (system stops working suddenly).

Apart from ARIANE rockets and Air Traffic Control systems, it is also used in airplanes, medical technology, the PANAVIA Tornado, the Eurofighter Typhoon, Eurocopter Tigre and NH-90 systems, and about any mission-critical system a simple reboot on failure is no option. Since Ada95, there are Object Oriented addition to Ada. A superset of Ada called SPARK that can be compiled in normal Ada compilers (the extra instructions are inside comments) is for highly verified code; AdaDoc in Ada2012 offers a JavaDoc-like Documentation generation system.

The Cromemco CR-250 Motorola 68000 S-100 machine was in widespread use as USAF Mission Support System (1986-1990), so a CP/M Ada83 compiler should be available.

Tools

IDE :

  • Xilinx webpack
  • Quartus web edition (Altera)

Development starter-kit :

Final platform (can be also used to develop) :

Books

  • Conception de circuits en VHDL et VHDL-AMS / Principes et méthodologie / Collection POLYTECH / Cépaduès-éditions / D. HOUZET L. BARRANDON
  • VHDL-AMS / Applications et enjeux industiels / Cours et exercices corrigés / 2e et 3e cycles écoles d'ingénieurs/ DUNOD / Yannick Hervé

VHDL-AMS is theorical, it is about using an analog version of VHDL not running in FPGA. But VHDL-AMS books does cover also VHDL (if an author of book does understand VHDL-AMS, sure he does understand VHDL perfectly.....)

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