Difference between revisions of "ASIC"

Application-Specific Integrated Circuit (ASIC)

An ASIC is an especially manufactured custom chip designed to fulfill special functions.

The main reason is to perform special tasks or combine different electronic components into a single Integrated Circuit (chip). This chip is not commonly available (COTS), but has to be ordered as a genuine part, prices dictated by the seller.

After a seller goes out of business or stops supporting a product line, before IPs (Instruction set Processors) like CPLD or FPGA, they essentially became unavailable. Commodore used a plethora of ASICs in their machines (VIC, SID, PAULA,......); MSX or the IBM PC/XT/AT were the opposite in using only COTS components, making it easy for third parties to offer parts (or to re-build and repair the computers for as long as the COTS chip was still available or a backwards-compatible component exists).

The Amstrad CPC used one custom chip: the video Gate Array (also called VGA – no connection with the Video PC standard).

Later CPC cost down series included a "pre-ASIC"-called ASIC to merge the VGA and the CRTC.

The Amstrad Plus included a "second heart" simply referred as the ASIC.

CPC+ ASIC's part number is 40489

CPC+ ASIC emulates the following chips:

• CRTC 6845
• Gate Array
• PAL (128K RAM paging)
• 8255 PPI
• Printer Port Data and Strobe
• Floppy Motor enable flip-flop, Floppy Address decoding (FDC chip Select)

This Amstrad Plus ASIC performs many additional features that the old CPC series couldn't: the "Plus Features".

• 12-bit colour palette
• Hardware sprites
• Vertical and horizontal per-pixel hardware soft scrolling (in complement with register 12&13 of the CRTC)
• Screen splitting
• Programmable raster interrupts
• Vectored interrupts
• DMA sound channels
• Specific ROM switching
• 8-bit printer port (with bit3 of CRTC register 12)
• Analog joystick port

Analog joystick axes are unsigned 6-bit values. Bits7..6 are always 0.

A colour in the palette is coded in 2 bytes:

• For first byte, bits7..4 are blue value, bits3..0 are red value
• For second byte, bits7..4 are ignored, bits3..0 are green value

Sprites are prioritized so that the border has the highest priority, followed by sprites 0 to 15 in sequence, then the main screen data.

There is only one pixel per byte in sprite image data. Bits3..0 of each byte define the palette index for this pixel (a value of 0 means transparent colour). Bits7..4 are ignored.

Each sprite magnification is coded in 1 byte:

• bits7..3 are ignored
• bits3..2 are X magnification (00 = not displayed, 01 = x1, 10 = x2, 11 = x4)
• bits1..0 are Y magnification (00 = not displayed, 01 = x1, 10 = x2, 11 = x4)

Sprites will be displayed at coordinates based on the internal counters of the CRTC. Sprite X coordinate is based on HCC. Sprite Y coordinate is based on VCC and VLC.

The SSCR register (at address 6804h) controls soft scrolling by pixels rather than by characters. Setting this register to 0 (the default value at power-up) disables the soft scroll feature. The soft scrolling mechanism affects the entire main screen, regardless of the split screen feature, but does not affect sprites.

• Bits3..0 of SSCR define a horizontal delay between 0 and 15 high-resolution (mode 2) pixels, shifting the screen image to the right by the programmed value. This causes pixels to be lost behind the right border and random data to appear on the left. Also the programmer must ensure that the delay value is a multiple of the number of bits per pixel.
• Bits6..4 of SSCR are summed to the least significant 3 bits of the scan line address, determining which of the eight 2k blocks contains the data for the first scan line on the screen. This shifts the display up by the programmed number of scan lines, causing the first lines to be lost and extra lines to appear at the bottom.
• Bit7 of SSCR, when set, extends the border to cover the first 2 bytes (16 high-resolution pixels) of each scan line, masking bad data caused by the horizontal soft scroll. When using horizontal soft scroll, always set this bit to maintain consistent screen width.

The SPLT register (at address 6801h) specifies the scan line where the screen split occurs. Setting this register to 0 (the default value at power-up) disables the split screen feature.

The SSA register (high byte at address 6802h and low byte at address 6803h) defines the starting address in memory for displaying the lower part of the screen.

SSA works similarly to the duo R12/R13 in the CRTC and allows the lower part of the screen to be sourced from a different memory area and be scrolled independently. However, note that the soft scrolling register SSCR acts on the whole screen regardless.

The PRI register (at address 6800h) specifies the scan line where the interrupt occurs. The interrupt will occur at the end of that scan line. Setting this register to 0 (the default value at power-up) reverts to the classic Gate Array R52 raster interrupt system instead.

PRI can be reprogrammed as required to produce multiple interrupts per frame.

Also PRI can trigger interrupts beyond the first 256 lines. For example, when PRI = 10, an interrupt will be triggered at line 10 but also at line 266.

The available commands are:

Note that:

• REPEAT Loops cannot be nested. Only one is allowed to be active per instruction stream at any time.
• REPEAT 0 and PAUSE 0 instructions have no effect, i.e. they are equivalent to NOP.
• Control group (4xxxh) instructions can be logically ORed to produce more complex instructions, e.g. INT|STOP = 4030h = Interrupt and Stop.
• The STOP instruction will leave the source address register (SAR) pointing to the next instruction, so that the instruction stream can be continued after CPU intervention.
• The argument field (N) of the REPEAT instruction is actually the number of times the loop is taken. The block of code between REPEAT and LOOP instructions is therefore executed N+1 times.

These instructions are encoded in little-endian (LSB byte first). They must be located in Base 64k RAM and aligned to word boundary (the address of first byte must be even).

Instruction codes 4xxxh are partially decoded by the DMA controller. For example, the instruction code CFCFh is equivalent to 4001h.

Each DMA channel fetch one 16-bit instruction during horizontal retrace time. Once the 3 instructions have been captured, they are then executed sequentially.

All instructions execute in 1 cycle, except LOAD which requires at least 8 cycles. An extra cycle is added to a LOAD if the CPU is accessing the PPI, or 2 extra cycles if the CPU access was itself a PSG register write.

A pause prescaler register (PPR) is available for each channel to define the pause unit. It is expressed in number of HSYNCs.

The DMA control and status register DCSR (at address 6C0Fh) controls which channels are currently enabled, and also tells the CPU which channel is interrupting:

• Bits2..0 are the channel enable bits. When set to "1" it enables the corresponding DMA channel. It can be set by the CPU, and cleared by either the CPU, a STOP instruction, or power-on reset.
• Bits7..4 are the interrupt bits. An interrupt bit is set to "0" when the corresponding channel is requesting an interrupt, and cleared when the CPU writes a "1" to the appropriate bit.
• The INT signal of the ASIC is the compositing of all the interrupt bits of DCSR by using the AND function. INT is active at "0" if at least one of the interrupt bits is "0".

The ASIC always provides an interrupt vector to the CPU on INT ACK.

The register IVR (at address 6805h) supplies the top 5 bits of the vector provided to the CPU. IVR is undefined at reset except that bit0 will be set to 1. Therefore, before placing the CPU in vectored interrupt mode, always set up the IVR so that the top 5 bits are defined.

Bits2..1 of the IVR register are unused.

Bit0 of the IVR register controls whether DMA channel interrupts are automatically cleared. Raster interrupts are always automatically cleared regardless of this setting.

Interrupts are prioritized in a fixed sequence. The raster interrupt has the highest priority, followed by DMA channels 2 down to 0 respectively.

Interrupt vector used on Z80 IM2 mode

The Amstrad Plus ASIC improved a lot of the old CPC's capability. Yet this was a bit flawed.

• Despite removing some tasks from the CPU (Z80), ASIC registers are mapped onto memory from #4000 to #7FFF range prior to other type of memory (RAM or ROM). That means this memory range is not accessible when ASIC registers are paged.

• PPI emulation is not correct as the original 8255 does not need validation. On ASIC emulation, this validation is needed so some programs written for "old CPCs" will not be able to get keyboard state.

• Z80 IM2 mode is bugged. In this mode, the Z80 I register gives the high byte for vector table. ASIC gives the low byte from IVR and the devices that generate interrupt (raster and DMAs channels). ASIC may generate a bad value and make the raster interrupt routine called instead of DMA0 routine if the Z80 is running particular portions of memory. See Plus Vectored Interrupt Bug for more details.

• There is a conflict between programmable interrupts and some CRTC settings (line screen split). That will cause the RAM refresh to stop and the memory content will be quickly corrupted causing machine crash.

• Reducing horizontal blanking could cause another internal conflict when using DMA lists. In the worst case, this conflict can cause irreversible damage to the ASIC.

• Original CPC colors emulation is not correct.

• ASIC at Wikipedia General information on ASICs.

• Asic and Plus features at Unofficial CPC ressources 1.4
• Asic and Plus features at Unofficial CPC ressources 1.5
• Extra Plus Hardware Information
• Quasar ASIC documentation (in french)

• Arnold V specs
• Arnold V Specs Revised
• Extra CPC Plus Hardware Information

• ASIC I/O page
• Programming:Unlocking ASIC
• B-ASIC

• CRTC
• Gate Array