Difference between revisions of "CRTC"

Latest revision as of 07:19, 3 July 2024

The CRTC (Cathode Ray Tube Controller) helps to generate the video signal of the Amstrad CPC.

NOTE: This document describes the functionality in terms of the CPC with its separate CRTC and Gate-Array. The Plus has both integrated into the same IC, but could be considered to have two functional blocks, one for CRTC and one for Gate-Array. In this document the term 'Gate-Array' is used, but this also applies to the ASIC.

Overview

The 6845 Cathode Ray Tube Controller (CRTC) is a programmable IC used to generate video displays. This IC is used in a variety of computers including the Amstrad CPC, Amstrad CPC+ and KC Compact.

The CRTC was a common part available from many different manufacturers. During the life of the CPC, Amstrad sourced the CRTC from various manufacturers.

All ICs used were based on the same design but have a different implementation. As a result they do not operate identically in all situations. This document highlights these differences.

This table lists the known ICs used, with their part number, manufacturer and type number.

NOTES

1. The CRTC functionality is integrated into the CPC+ ASIC. This type exists only in the CPC464+,CPC6128+ and GX4000.

2. This type exists in "cost-down" CPC464 and CPC6128 systems. In the "cost-down" the CRTC functionality is integrated into a single ASIC IC. This ASIC is often refered to as the "Pre-ASIC" because it preceeded the CPC+ ASIC. The CRTC functionality of the Pre-ASIC is almost identical to the CRTC within the ASIC.

3. In the Amstrad community each 6845 implementation has been assigned a type number. This type identifies a group of implementations which operate in exactly the same way.

As far as I know, the type number system was originally used by demo programmers.

It is possible to detect the 6845 present using software methods, and this is done to:

• warn that the software was not designed for the detected 6845 and may function incorrectly,
• to adapt the software so that it will run with the detected 6845
• In most cases, the type of the detected 6845 is reported.

4. As far as I know, the KC compact used HD6845R only.

Timings and relating with Z80 instructions count

Some informations like : how many Z80 instructions can I fit within a scan line ? Within a screen ? Etc... See http://www.cpcwiki.eu/forum/programming/frame-flyback-and-interrupts/msg25106/#msg25106 (To be extracted/edited to conform to wiki good practices).

Programming

The 6845 is selected when bit 14 of the I/O port address is set to "0". Bit 9 and 8 of the I/O port address define the function to access. The remaining bits can be any value, but it is adviseable to set these to "1" to avoid conflict with other devices in the system.

The recommended I/O port addresses are

NOTE

1. The function of these I/O ports is dependant on the CRTC type

2. The CRTC is not connected to the CPU's RD and WR pins, so the CRTC is not aware of the CPU bus I/O direction. Therefore, if you perform an IN instruction to the select or write functions, it will write data to the CRTC from the current data on the bus.

Addressing

The video memory address VMA of the Gate Array is constructed from the CRTC MA and RA signals.

CRTC generates the address, Gate Array reads the data and converts it to pixels based on its current graphics mode and palette.

CRTC pins RA3, RA4, MA10, MA11 are not connected on CPC.

CUDISP (aka CURSOR)

CUDISP (Cursor Display) signal defines the hardware cursor.

CRTC pin CUDISP is not connected to the Gate Array, so it has no effect on a barebone CPC or Plus machine.

However, this signal is provided to the expansion port. And it is used by the PlayCity and Play2CPC expansions.

DISPTMG (aka Display Enable)

DISPTMG (Display Timing) signal defines the border. When DISPTMG is "0" the border colour is output by the Gate Array to the display.

The border has higher priority than pixels but lower priority than the black colour output when HSYNC/VSYNC are active.

The DISPTMG can be forced to 0 by using R8 (DISPTMG Skew) on type 0,3 and 4 or by setting R6=0 on type 1. It is not possible to force the DISPTMG on type 2.

HSYNC and VSYNC

On CPC, HSYNC and VSYNC from the CRTC are passed to the Gate Array for further modification. See its wiki page.

The HSYNC width value is interpreted differently between CRTCs. On CRTCs 0/1, if 0 is programmed no HSYNC is generated. On CRTCs 2/3/4, if 0 is programmed this gives a HSYNC width of 16.

CRTCs 1/2 have a fixed VSYNC width value of 16. VSYNC width can be configured with Register 3 on CRTCs 0/3/4. If 0 is programmed this gives 16 lines of VSYNC.

The bit 0 of port B of the PPI changes to 1 as soon as the VSYNC signal is produced by the CRTC.

CRTC registers

The Internal registers of the 6845 are:

registers 18-31 read as 0, on type 0 and 2. registers 18-30 read as 0 on type1, register 31 reads as 0xff.

Details about Reg. 12 and Reg. 13 specifically:

 .------- REG 12 --------.   .------- REG 13 --------.
 |                       |   |                       |
  15 14 13 12 11 10 09 08     07 06 05 04 03 02 01 00
 .--.--.--.--.--.--.--.--.   .--.--.--.--.--.--.--.--.
 |X |X |  |  |  |  |  |  |   |  |  |  |  |  |  |  |  |
 '--'--'--'--'--'--'--'--'   '--'--'--'--'--'--'--'--'
       '--.--'--.--'---------------.-----------------'
          |     |                  |
          |     |                  '------> Offset for setting
          |     |                           videoram 
          |     |                           (1024 positions)
          |     |                           Bits 0..9
          |     |
          |     '-------------------------> Video Buffer : note (1)
          |
          '-------------------------------> Video Page : note (2)
 note (1)                 note (2)
 .--.--.--------------.  .--.--.---------------.
 |11|10| Video Buffer |  |13|12|   Video Page  |
 |--|--|--------------|  |--|--|---------------|
 | 0| 0|     16Ko     |  | 0| 0|  0000 - 3FFF  |
 |--|--|--------------|  |--|--|---------------|
 | 0| 1|     16Ko     |  | 0| 1|  4000 - 7FFF  |
 |--|--|--------------|  |--|--|---------------|
 | 1| 0|     16Ko     |  | 1| 0|  8000 - BFFF  |
 |--|--|--------------|  |--|--|---------------|
 | 1| 1|     32Ko     |  | 1| 1|  C000 - FFFF  |
 '--'--'--------------'  '--'--'---------------'

So, it's possible to use 32KB screen size (used for overscan) by setting bits 11 and 10 both to 1 (of Register 12). Bits MA11 and MA10 of the address generated by the CRTC are not written on the address bus to access video memory; settings both bits to 1 is the only way to cause a carry to bit MA12 when address pass over the end of current video page to change the memory address to the next video page.

CRTC register differences

The following tables list the functions that can be accessed for each type:

Type 0

Type 1

Type 2

Type 3 and 4

It is not possible to read from all the internal registers, this table shows the read/write status of each register for each type:

Notes

• On types 0 and 1, if a Write Only register is read from, "0" is returned.

• CRTC types 3 and 4 are identical in every way, except for the unlocking mechanism, split-screen and 8-bit printer port functionalities specific to the ASIC.

• See the document "Extra CPC Plus Hardware Information" for more details.

Horizontal and Vertical Sync (R3)

Type 0:

• Bits 7..4 define Vertical Sync Width. If 0 is programmed this gives 16 lines of VSYNC.
• Bits 3..0 define Horizontal Sync Width. If 0 is programmed no HSYNC is generated.

Type 1:

• Bits 7..4 are ignored. Vertical Sync is fixed at 16 lines.
• Bits 3..0 define Horizontal Sync Width. If 0 is programmed no HSYNC is generated.

Type 2:

• Bits 7..4 are ignored. Vertical Sync is fixed at 16 lines.
• Bits 3..0 define Horizontal Sync Width. If 0 is programmed this gives a HSYNC width of 16.

Types 3/4:

• Bits 7..4 define Vertical Sync Width. If 0 is programmed this gives 16 lines of VSYNC.
• Bits 3..0 define Horizontal Sync Width. If 0 is programmed this gives a HSYNC width of 16.

Interlace and Skew (R8)

Types 0/3/4:

• Bits 7..6 define the skew (delay) of the CUDISP signal (00 = Non-skew ; 01 = One-character skew ; 10 = Two-character skew ; 11 = Non-output).
• Bits 5..4 define the skew (delay) of the DISPTMG signal (00 = Non-skew ; 01 = One-character skew ; 10 = Two-character skew ; 11 = Non-output).
• Bits 3..2 are ignored.
• Bits 1..0 define the interlace mode (00 = No Interlace; 01 = Interlace Sync; 10 = No Interlace; 11 = Interlace Sync and Video).

Types 1/2:

• Bits 7..2 are ignored.
• Bits 1..0 define the interlace mode.

2 interlace modes are available:

• In interlace sync mode, the same information is painted in both fields to enhance readability. In this mode, reprogramming the CRTC is not necessary
• In interlace sync and video mode, alternating lines are displayed in the even and odd field to double the resolution. In this mode, it is necessary to reprogram the CRTC as if we were building a frame of 624 lines. The 625th line is managed automatically by the CRTC

R31 on Type 1

R31 is described in the UM6845R documentation as "Dummy Register".

Its use is described in the documentation for the Rockwell R6545 in combination with R18, R19 and R8 and the Status Register.

In the UM6845R it appears to have no effect. Reading and writing does nothing. Reading it returns 0x0ff.

R31 doesn't exist on types 0,2,3,4.

Status register on Type 1

The UM6845R has a status register that can be read using port &BExx.

Bit 6 is set to 1 if there is a strobe input to the /LPEN signal. It is cleared to 0 when either R17 or R16 (LPEN address) of the CRTC are read. It signals there is a valid LPEN input. On my CPC (arnoldemu) with UM6845R, it is triggered at power on, R17 and R16 have the values 0 when read.

Bit 5 is set to 1 when CRTC is in "vertical blanking". Vertical blanking is when the vertical border is active. i.e. VCC>=R6.

It is cleared when the frame is started (VCC=0). It is not directly related to the DISPTMG output (used by the CPC to display the border colour) because that output is a combination of horizontal and vertical blanking. This bit will be 0 when pixels are being displayed.

All the other bits read as 0 and don't have any function.

R10/R11 on ASIC/Pre-ASIC

The cursor raster registers R10/R11 act as status registers when read on Types 3 & 4. They behave as normal cursor raster registers upon write.

Reading from CRTC registers on ASIC/Pre-ASIC

On CRTC Types 3 and 4, only the 3 least significant bits of the selected register number are considered to read a register according to the following table:

Therefore, as an example, reading register 4 will give the same result as reading register 12 or 20.

CRTC Type Detection

10 MODE 1:' Reinitialize screen
20 OUT &BC00,31:IF INP(&BF00)=255 THEN PRINT"crtc 1":END
30 OUT &BC00,12:IF INP(&BF00)=0 THEN PRINT"crtc 2":END
40 OUT &BC00,20:IF INP(&BF00)=0 THEN PRINT"crtc 0":END
50 PRINT"crtc 3/4"

CRTC Timing Diagrams

Internal Counters

No matter its type, the CRTC never buffers its counters.

The only value that is saved in a buffer in the CRTC is the video pointer MA because it is reloaded at each raster line start.

R12/R13 is loaded only once per frame, in MA and MA', at the first raster line start of the frame. The counter MA is then reloaded with the value of MA' at each raster line start. And at each new character line start, MA' captures the current value of MA.

The exception is the CRTC 1 for which MA is reloaded at each raster line start with R12/R13 instead of MA' as long as VCC=0.

This is a major source of incompatibility if the programmer does not take care of this discrepancy. In demos and games, to make a display compatible with all CRTCs, program R12/R13 when VCC!=0. This will then take effect at the next frame start.

CRTC counter differences

VSC (C3h) overflow

During a VSYNC on CRTCs 0/3/4, if VSYNC Width (R3h) is changed with a value less than the current VSC, then VSC overflows and will continue to count up to its maximum value (15) before looping back and counting up again until it reaches the new value of R3h.

On CRTCs 1/2, the VSYNC width is fixed to 16 characters. It is not possible to modify it. Therefore, VSC cannot be overflowed.

HSC (C3l) overflow

During an HSYNC, if HSYNC Width (R3l) is changed with a value less than the current HSC, then HSC overflows and will continue to count up to its maximum value (15) before looping back and counting up again until it reaches the new value of R3l.

The only exception is for CRTC 1 with a value of 0, which immediately cancels the current HSYNC.

VCC (C4) overflow

On all CRTCs, if Vertical Total (R4) is changed with a value less than VCC, then:

• if this update was done when VCC < R4, then VCC overflows and will continue to count up to its maximum value (127) before looping back and counting up again until it reaches the new value of R4
• if this update was done when VCC = R4, the current character line was already decided to be the last one of the current frame. No update to R4 will make the CRTC change its mind for the current frame

The only exception when VCC = R4 is for CRTC 1 with a value of 0, which will cause VCC to overflow.

HCC (C0) overflow

If Horizontal Total (R0) is changed with a value less than the current HCC, then:

• on CRTCs 0/1/2, HCC overflows and will count up to its maximum value (255) before looping back and counting up again until it reaches the new value of R0
• on CRTCs 3/4, the current line is considered finished and HCC is immediately reset to 0 on the next line

VLC (C9) overflow

If Number of Scan Lines (R9) is changed with a value less than the current VLC, then:

• on CRTCs 0/1/2, VLC overflows and will count up to its maximum value (31) before looping back and counting up again until it reaches the new value of R9
• on CRTCs 3/4, the current line is considered the last one of this CRTC character and VLC will reset to 0 on the next line

VTAC (C5/C9) overflow

During vertical adjustment mode, if Vertical Total Adjust (R5) is changed with a value less than the current VTAC, then:

• on CRTCs 0/1/2, VTAC overflows and will continue to count up to its maximum value (31) before looping back and counting up again until it reaches the new value of R5
• on CRTCs 3/4, the current line is considered the last one of the current frame and vertical adjustment will end

Vertical Adjustment mode

On CRTCs 0/1/2, this mode increments VCC and so VCC goes beyond R4.

On CRTCs 3/4, this mode does not increment VCC and so VCC stays equal to R4.

Hitachi Block Diagram

UMC Block Diagram

Motorola Block Diagram

Datasheets

• HD6845S (Hitachi) aka Type 0
• UM6845 (UMC) aka Type 0
• UM6845R (UMC) aka Type 1
• MC6845 (Motorola) aka Type 2 Other datasheet version
• AMS40489 (Amstrad) aka Type 3
• AMS40226 (Amstrad) aka Type 4
• HD6345 (Hitachi) aka Type 5 - Upgraded pin-compatible CRTC chip with advanced functionalities Upgrading the CPC to HD6345

Unused clones

• CM607P a Bulgarian clone made in Pravetz factory
• EF6845 by Thomson Semiconductors
• UM6845E by UMC
• F6845 by Fairchild
• CRTC 6545 (MOS, Rockwell, Synertek) is pin-compatible with the 6845 and only has minor differences
• BeebFpga MiSTer OpenCores Verilog/VHDL implementations of the 6845

Tools about CRTC

• some BASIC tools to detect CRTC types 0-1-2 and show some effects by Elmar Krieger (DSK for Emulators)
• File:Shaker26.dsk Shaker - Suite of CRTC tests associated with the CPC CRTC compendium (many of them will not work correctly on emulators and that was the purpose of the tests, to help create more compatible emulation)
• File:Shaker addon.dsk Shaker Add-On (Pixel 1 Hard Scroll / Vertical Rupture all Crtc)

Links

• Wikipedia on the CRTC
• CRTC documentation from Grimware
• Quasar CRTC documentation (in french)
• Differences between CRTC types
• Media:Dossier Rupture(Gozeur Paradox).pdf
• Media:Dossier CRTC(Ramlaid Mortel).pdf Les entrailles du CRTC
• Leçons CRTC (CheshireCat)
• Media:ACCC1.8-EN.pdf Media:ACCC1.8-FR.pdf CPC CRTC Compendium - Latest (04/2024!) document containing in-depth info about CRTC programming on CPC.

Related pages

• Gate Array

• ASIC

• Video modes

• Synchronising with the CRTC and display : technic and details on the relationship between Gate Array and CRTC.