Difference between revisions of "FPGA"
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FPGA (field-programmable gate array) | FPGA (field-programmable gate array) | ||
| − | This is a reprogrammable | + | This is a reprogrammable [[COTS]] Instruction set Processor (IP). It consists of a re-programmable ("FP") Gate Array (GA), i.e. a [[FET]] (Field-Effect Transistor) array where the transistors can be set by the FET Gate to "conduct" or "resist". This can flexibly simulate many different logical ICs. |
| + | == FPGA basics == | ||
You know what a "truth table" is ? Here a example :<br /> | You know what a "truth table" is ? Here a example :<br /> | ||
'''XOR''' truth table : | '''XOR''' truth table : | ||
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1 1 | 0 | 1 1 | 0 | ||
| − | In a truth table you have got 2 input wires, and 1 output wires. | + | In a truth table you have got eg. 2 input wires, and 1 output wires. |
| − | In | + | A FPGA is programmed by a LUT (Look-Up Table) that has to be loaded into volatile memory at power-up. In a FPGA LUT you have got 10,000,000,000,000,000 input/output wires. |
| − | As it is complex to feed the table values, | + | As it is complex to feed the table values, special languages (HDL - Hardware Description Language) are used to feed them : [[VHDL]] (and -blech!!!- verilog) |
| − | GA in Amstrad is an ASIC. | + | The Gate Array (GA) in Amstrad graphics is an [[ASIC]]. |
| + | |||
| + | == CPLD == | ||
| + | [[CPLD]] are re-programmable IPs that are faster and non-volatile; however, they are not as versatile as FPGAs, so FPGAs offer more possibilities closed to CPLDs. They consist of AND- and OR-matrices that can be connected to a signal or the inverted signal (NOT); those [[minterm]]s can construct all other logical equasions (to the boundaries of the chip). | ||
| + | |||
| + | Common CPLDs are made by Atheros (now part of Intel) and Altera. | ||
Revision as of 23:25, 8 March 2017
FPGA (field-programmable gate array)
This is a reprogrammable COTS Instruction set Processor (IP). It consists of a re-programmable ("FP") Gate Array (GA), i.e. a FET (Field-Effect Transistor) array where the transistors can be set by the FET Gate to "conduct" or "resist". This can flexibly simulate many different logical ICs.
FPGA basics
You know what a "truth table" is ? Here a example :
XOR truth table :
A B | C 0 0 | 0 0 1 | 1 1 0 | 1 1 1 | 0
In a truth table you have got eg. 2 input wires, and 1 output wires.
A FPGA is programmed by a LUT (Look-Up Table) that has to be loaded into volatile memory at power-up. In a FPGA LUT you have got 10,000,000,000,000,000 input/output wires.
As it is complex to feed the table values, special languages (HDL - Hardware Description Language) are used to feed them : VHDL (and -blech!!!- verilog)
The Gate Array (GA) in Amstrad graphics is an ASIC.
CPLD
CPLD are re-programmable IPs that are faster and non-volatile; however, they are not as versatile as FPGAs, so FPGAs offer more possibilities closed to CPLDs. They consist of AND- and OR-matrices that can be connected to a signal or the inverted signal (NOT); those minterms can construct all other logical equasions (to the boundaries of the chip).
Common CPLDs are made by Atheros (now part of Intel) and Altera.
