Difference between revisions of "Schneiderware Summary"

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(Datasheets)
(Datasheets)
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* [[Media:8253.pdf|8253 Datasheet]] - 8253 Timer Datasheet (slower clock, write-only control registers)
 
* [[Media:8253.pdf|8253 Datasheet]] - 8253 Timer Datasheet (slower clock, write-only control registers)
 
* [[Media:8254.pdf|8254 Datasheet]] - 8254 Timer Datasheet (faster clock, read/write-able control registers, otherwise compatible with 8253)
 
* [[Media:8254.pdf|8254 Datasheet]] - 8254 Timer Datasheet (faster clock, read/write-able control registers, otherwise compatible with 8253)
* [[Media:PPI M5L8255AP-5.pdf||8255 Datasheet]] - PPI Datasheet (Mitsubishi)
+
* [[Media:PPI M5L8255AP-5.pdf|8255 Datasheet]] - PPI Datasheet (Mitsubishi)
 
* [[Media:ADC0848 Datasheet.pdf|ADC0848 Datasheet.pdf]] - 8 channel A/D converter
 
* [[Media:ADC0848 Datasheet.pdf|ADC0848 Datasheet.pdf]] - 8 channel A/D converter
 
* [[Media:DAC0832 Datasheet.pdf|DAC0832 Datasheet.pdf]] - 1 channel D/A converter
 
* [[Media:DAC0832 Datasheet.pdf|DAC0832 Datasheet.pdf]] - 1 channel D/A converter
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* [[Media:L200 Datasheet.pdf|L200 Datasheet]] - 5-pin variable-voltage converter (seems to be used by an alternate version of the power supply)
 
* [[Media:L200 Datasheet.pdf|L200 Datasheet]] - 5-pin variable-voltage converter (seems to be used by an alternate version of the power supply)
 
* [[Media:M5832 Datasheet.pdf|M5832 Datasheet]] - Real time clock
 
* [[Media:M5832 Datasheet.pdf|M5832 Datasheet]] - Real time clock
 +
 +
Info on various ECB Bus variants can be found here: [[EBC Bus]].

Revision as of 15:30, 30 September 2010

This page contains a summary of Schneiderware related info. For details refer to the separate pages (links are found on the Schneiderware page.

I/O Port Summary

Address (default) Address (alternate) Usage
DFxxh N/A Schneiderware RAM/EPROM - Expansion ROM bank number (W)
Battery-backed SRAM and/or EPROM are selected when the bank-number matches the jumper-selected values; the memory is then mapped to C000h..FFFFh (in case of READing one must also enable upper ROM via Gate Array). The bank number decoding is a bit strange:
  • EPROM/Read bank: All 8 bits decoded (bank 00h..FFh)
  • SRAM/Read bank: Only lower 4 bits decoded (bank X0h..XFh)
  • SRAM/Write bank: Only lower 4 bits decoded (bank X0h..XFh)

The SRAM/Write mode doesn't disable the internal RAM in the CPC, so writes are going both to SRAM and normal RAM at C000-FFFF, that no matter if upper ROM is enabled/disabled via Gate Array; the author recommended to map VRAM to 4000-7FFF via CRTC registers, in order to prevent video dirt during writing.

F8E0h F8F0h (later redefined to F8E4h) Schneiderware Centronics Port 8255 PPI Port A (data)
F8E1h F8F1h (later redefined to F8E5h) Schneiderware Centronics Port 8255 PPI Port B (unused)
F8E2h F8F2h (later redefined to F8E6h) Schneiderware Centronics Port 8255 PPI Port C (busy/strobe)
(bit7=busy, bit6-1=unused, bit0=strobe; strobe is externally inverted)
(autolf is wired to GND, all other control/status signals are not connected)
F8E3h F8F3h (later redefined to F8E7h) Schneiderware Centronics Port 8255 PPI Control
F8E8h F8F0h, F8F8h Schneiderware Uni-PIO 8255 PPI #1 Port A (without pull-ups, with red LEDs)
F8E9h F8F1h, F8F9h Schneiderware Uni-PIO 8255 PPI #1 Port B (with pull-ups and green LEDs)
F8EAh F8F2h, F8FAh Schneiderware Uni-PIO 8255 PPI #1 Port C (lower 4bit without pull-ups and red LEDs, upper 4bit with pull-ups and green LEDs)
F8EBh F8F3h, F8FBh Schneiderware Uni-PIO 8255 PPI #1 Control
F8ECh F8F4h, F8FCh Schneiderware Uni-PIO 8255 PPI #2 Port A (without pull-ups or LEDs)
F8EDh F8F5h, F8FDh Schneiderware Uni-PIO 8255 PPI #2 Port B (without pull-ups or LEDs)
F8EEh F8F6h, F8FEh Schneiderware Uni-PIO 8255 PPI #2 Port C (without pull-ups or LEDs)
F8EFh F8F7h, F8FFh Schneiderware Uni-PIO 8255 PPI #2 Control
F9E0h F9E2h Schneiderware V/24 Interface 8251 USART Data
F9E1h F9E3h Schneiderware V/24 Interface 8251 USART Control
F9ECh F9E8h Schneiderware V/24 Interface 8253 Timer 0 (TX clock)
F9EDh F9E9h Schneiderware V/24 Interface 8253 Timer 1 (RX clock)
F9EEh F9EAh Schneiderware V/24 Interface 8253 Timer 2 (unused)
F9EFh F9EBh Schneiderware V/24 Interface 8253 Timer Control
Note: Timer clock input is jumper select-able: 2MHz (default), or 1MHz
FAE0h N/A Schneiderware Analog Converter ADC 0848 A/D Converter (R/W)
Read: Get 8bit data from selected channel
Write: Select channel & mode; bit0..2=channel (0..7), bit3..4=mode, bit5-7=unused
  • Mode 0 (or 1) - Differential: Plus=Channel(N), Minus=Channel(N XOR 1)
  • Mode 2 - Single-Ended: Plus=Channel(N) and Minus=AGND
  • Mode 3 - Pseudo-Differential: Plus=Channel(N) and Minus=Channel(7)
FAE1h N/A Schneiderware Analog Converter DAC 0832 D/A Converter #1 (W)
Write: 8bit data
FAE2h N/A Schneiderware Analog Converter DAC 0832 D/A Converter #2 (W)
Write: 8bit data
FAF0h N/A Schneiderware EPROM Burner 8255 PPI #1 Port A (Data, 8bit)
FAF1h N/A Schneiderware EPROM Burner 8255 PPI #1 Port B (Address LSBs, 8bit)
FAF2h N/A Schneiderware EPROM Burner 8255 PPI #1 Port C (Address MSBs, 7bit; bit7=unused)
FAF3h N/A Schneiderware EPROM Burner 8255 PPI #1 Control
FAF4h N/A Schneiderware EPROM Burner 8255 PPI #2 Port A (bit0-7=unused)
FAF5h N/A Schneiderware EPROM Burner 8255 PPI #2 Port B (bit0-5=unused, bit6=Red LED, bit7=Green LED)
FAF6h N/A Schneiderware EPROM Burner 8255 PPI #2 Port C (programming signals, 8bit)
FAF7h N/A Schneiderware EPROM Burner 8255 PPI #2 Control
FBE2h BUGGED:FBE1h Schneiderware Real Time Clock Index/Control (W)
FBE3h BUGGED:FBE2h Schneiderware Real Time Clock Data 4bit (W)
FBE4h BUGGED:FBE3h Schneiderware Real Time Clock Data 4bit (R)

Schematics

Pictures

Software

Databoxes: UHR8000 RTC-RAM-driver in 10-1986 (hex listing, plus Hisoft Devpac source code) (caution this version uses incorrect I/O addresses FBE1-FBE3), UHRC000X RTC-ROM-driver in 4-1987 (this version uses correct I/O addresses FBE2-FBE4). Uni-PIO examples in 12-1986 (=only a few basic lines). There seem to be no Centronics and V/24 drivers included in databoxes.

Datasheets

Info on various ECB Bus variants can be found here: EBC Bus.