Difference between revisions of "6850 ACIA chip"

Revision as of 07:08, 4 January 2010

MC6850 Asynchronous Communications Interface Adapter (ACIA) (24pin)

Usage in CPC

Used by [[||CPCI_RS232_Interface|CPCI]] (DIY german magazine CPC Schneider International):

 F8DCh CPCI Serial Interface MC6850 Control/Status Register (R/W)
 F8DDh CPCI Serial Interface MC6850 Data Register (R/W)
 Input CLK is 19.2kHz or 38.4kHz (manually selectable via switch)
 Status.Bit2 is always 0 in this circuit
 IRQ pin is not connected (can be read only by software, in Status.Bit7)

Used by KDS_Electronics_Serial_Interface:

 FBECh KDS RS232 6850 (reversed-bit-order) Control (W)
 FBEDh KDS RS232 6850 (reversed-bit-order) TX Data (W)
 FBEEh KDS RS232 6850 (reversed-bit-order) Status  (R)
 FBEFh KDS RS232 6850 (reversed-bit-order) RX Data (R)
 Caution: KDS has wired the 6850 chip's data bus incorrectly: D7 is D0,
 D6 is D1, etc. (so the bit order must be reversed by software).
 Input CLK is 2MHz with variable 16bit divider (programmable 8253 chip)

Used by AMSSIO (DIY by Martin Zacho):

 Port addresses and other details on AMSSIO are unknown

Registers

MC6850 Control Register (W)

 0-1  Baudrate (0=CLK/64, 1=CLK/16, 2=CLK/1, 3=RESET)
 2-4  Mode (0..7 = 7e2,7o2,7e1,7o1,8n2,8n1,8e1,8o1) (data/stop bits, parity)
 5-6  Transmit Interrupt/RTS/Break control (0..3)
       0 = Output /RTS=low,  and disable Tx Interrupt
       1 = Output /RTS=low,  and enable Tx Interrupt
       2 = Output /RTS=high, and disable Tx Interrupt
       3 = Output /RTS=low,  and disable Tx Interrupt, and send a Break
 7    Receive Interrupt (1=Enable on buffer full/buffer overrun)

MC6850 Status Register (R)

 0    Receive Data  (0=No data, 1=Data can be read)
 1    Transmit Data (0=Busy, 1=Ready/Empty, Data can be written)
 2    /DCD level
 3    /CTS level
 4    Receive Framing Error (1=Error)
 5    Receive Overrun Error (1=Error)
 6    Receive Parity Error  (1=Error)
 7    Interrupt Flag (see Control Bits 5-7) (IRQ pin is not connected)

MC6850 Data Register (R/W) Data can be read when Status.Bit0=1, and written when Status.Bit1=1.

 0-7  Data

Rx has a 1-stage fifo, plus 1 shift register (2 stages in total) Tx has a 1-stage fifo, plus 1 shift register (2 stages in total)