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/* Introduction */
The gate array is a specially designed chip exclusively for use in the Amstrad CPC and was designed by Amstrad plc.
In the CPC+ system, the functions of the Gate-Array are integrated into a single [[ASIC]]. When the ASIC is "locked", the extra features are not available and the ASIC operates the same as the Gate-Array in the CPC allowing programs written for the CPC to work on the Plus without modification. The ASIC must be "un-locked" to access the new features.
In the KC compact system, the functions of the Gate-Array are "emulated" in [[TTL logic ]] and by the [[Zilog Z8536 CIO]].
In the "cost-down" version of the CPC6128, the functions of the Gate-Array are integrated into a ASIC.
The Gate Array is described here, as it is in a standard CPC.
''What does it do?''
The Gate Array is responsible for the display (colour palette, resolution, horizontal and vertical sync), interrupt generation and memory arrangement.
