Difference between revisions of "8255"
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| + | It is advised that the remaining bits of the I/O address are set to "1" to avoid conflict with other devices. The recommended I/O addressess are: | ||
| − | + | {|{{Prettytable|width: 700px; font-size: 2em;}} | |
| + | |''I/O address''||''PPI Function'' | ||
| + | |- | ||
| + | |&F4xx||Port A data | ||
| + | |- | ||
| + | |&F5xx||Port B data | ||
| + | |- | ||
| + | |&F6xx||Port C data | ||
| + | |- | ||
| + | |&F7xx||Control | ||
| + | |- | ||
| + | |} | ||
| + | |||
| + | In the CPC+, the 8255 is integrated into the ASIC. The "emulation" is not complete and some functionality is not available. Please see the "Extra CPC+ documentation" for more information. | ||
| + | |||
| + | * Mode 1 (Strobed Input/Output) and Mode 2 (Bi-Directional Bus), as far as I know, are not used by any program, Mode 0 (Basic Input/Output) is always used. | ||
| + | |||
| + | === Port Usage === | ||
| + | |||
| + | NOTE | ||
| + | |||
| + | * If you are using the firmware, always return the operating modes and I/O state of the ports used to their settings below. The firmware expects the settings to be the same as given below and may operate incorrectly if they are not. | ||
| + | |||
| + | |||
| + | === PPI Port A === | ||
| + | |||
| + | Operating system settings: | ||
| + | |||
| + | * I/O Mode 0, | ||
| + | * Output | ||
| + | |||
| + | NOTE: | ||
| + | |||
| + | * For writing data to PSG all bits must be set to output, | ||
| + | * for reading data from PSG all bits must be set to input. | ||
| + | |||
| + | |||
| + | [Image:8255 ppi 1.jpg]] | ||
= Resources == | = Resources == | ||
Revision as of 04:07, 30 March 2008
The 8255 is a general purpose input/output IC. This document will describe it's role in the Amstrad CPC,CPC+ and KC compact systems. To understand it's full functions please read the datasheet.
In these systems it is connected to the AY-3-8912 Programmable Sound Generator (PSG), keyboard, cassette recorder, the VSYNC of the 6845 CRTC and the "busy" signal from the parallel port.
The PPI is selected when bit 11 of the I/O port address is set to "0", bits 9 and 8 then define the PPI function access as shown below:
| Bit 9 | Bit 8 | Description | Read/Write status |
| 0 | 0 | Port A Data | Read/Write |
| 0 | 1 | Port B Data | Read/Write |
| 1 | 0 | Port C Data | Read/Write |
| 1 | 1 | Control | Write Only |
It is advised that the remaining bits of the I/O address are set to "1" to avoid conflict with other devices. The recommended I/O addressess are:
| I/O address | PPI Function |
| &F4xx | Port A data |
| &F5xx | Port B data |
| &F6xx | Port C data |
| &F7xx | Control |
In the CPC+, the 8255 is integrated into the ASIC. The "emulation" is not complete and some functionality is not available. Please see the "Extra CPC+ documentation" for more information.
- Mode 1 (Strobed Input/Output) and Mode 2 (Bi-Directional Bus), as far as I know, are not used by any program, Mode 0 (Basic Input/Output) is always used.
Contents
Port Usage
NOTE
- If you are using the firmware, always return the operating modes and I/O state of the ports used to their settings below. The firmware expects the settings to be the same as given below and may operate incorrectly if they are not.
PPI Port A
Operating system settings:
- I/O Mode 0,
- Output
NOTE:
- For writing data to PSG all bits must be set to output,
- for reading data from PSG all bits must be set to input.
[Image:8255 ppi 1.jpg]]
Resources =
[[Media: |Datasheet of the 8255]]
