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The Programmable Sound Generator (PSG) is able to output three separate a sound channels chip designed by General Instrument (named Channel A, B and CGI)in 1978. Each channel can be The specific model used to output tones and/or white noisein the CPC is the AY-3-8912 chip.

== The PSG Registers ==is quite primitive. It is able to output a square wave and/or white noise in three separate sound channels (named Channel A, B and C).

The PSG has 16 readSome other 8-bit systems used more sophisticated soundchips such as the [https:/writeable data registers, and a write-only index register/youtu. Both the index and data registers are accessed through PIO Port Abe/7pONRbIHT_w C64 SID], depending on the current setting of the BC1 and BDIR bits in [[8255|PPIhttps://youtu.be/BANwL2sQ0DM NES APU]] Port C. The four possible combinations are: 0=inactive 2=write data 1=read data 3=write indexThe procedure to write data to a specific register is as follows: Write and the register number to [[8255|PPI]] Port A, set BC1https:/BDIR to Write Index - and back to Inactive/youtu. Now write the data to PIO Port A, set BC1be/BDIR to Write Data - and back to InactivemdjiWBYIqU Gameboy soundchip].

* == I/O Access == The PSG has 16 read/writeable data registers, and a write-only index register. While there are only 16 data registers, the index register is 8-bit, not 4-bit. The higher 4-bits of the index register are used as chip select. Both the index and data registers are accessed through [[8255|PPI Port A]], depending on the current setting of the BC1 and BDIR bits in [[8255|PPI Port C]]. The four possible combinations are: {| class="wikitable"|-!PPI Port C!BDIR!BC1!Function|-|00xxxxxx||0||0||Inactive|-|01xxxxxx||0||1||Read from selected PSG register|-|10xxxxxx||1||0||Write to selected PSG register|-|11xxxxxx||1||1||Select PSG register|} The procedure to write data to a specific PSG register from the PPI is quite tedious. It consists of the following steps:# Write the register number to PPI Port A# set BC1/BDIR to Select Register# and back to Inactive# Now write the data to PPI Port A# set BC1/BDIR to Write Data# and back to Inactive. You must use 3 OUTs to send a value to an AY register, even if you don't change registers in the meantime. [https://www.cpcwiki.eu/forum/programming/interesting-walkthrough-video-coding-a-pet-to-play-samples-at-60khz/msg250874/#msg250874 Source] So you have to enter the data on F4. Then on F6, select the type of data (bdir/bc1>>#10) and validate everything (bdir/bc1>>00). Otherwise, the data in other AY registers becomes corrupted quite quickly. Consult this article for more information: [[How to access the PSG via PPI]] <br> == PSG Registers ==

F = 4MHz 1MHz / 64 16 / nn ;with nn in range 1..4095 (nn=0 acts as nn=1)

F = 4MHz 1MHz / 64 16 / nn ;with nn in range 1..31 (nn=0 acts as nn=1)

F = 4MHz 1MHz / 64 16 / nn ;with nn in range 1..65535 (nn=0 acts as nn=1)

T = nn*1024 256 / 4MHz 1MHz ;with nn in range 1..65535 (256us .. 16.7 seconds)

Writing to this register (re-)starts the envelope. Additionally, Both components of the envelope's phase are reset. The first step of the envelope has full duration every time. It is never shorted. [https://forums.nesdev.org/viewtopic.php?p=236672#p236672 Source] The written value specifies the envelope shape, the four bits have the following meaning:

{| class="wikitable"|-! Binary !! Hex !! Shape!! Comment |-| 00XX || 00h-03h || <code>\_________ (</code> || same as 09h) |-| 01XX || 04h-07h || <code>/_________ (</code> || same as 0Fh) |-| 1000 || 08h || <code>\\\\\\\\\\</code> || |-| 1001 || 09h || <code>\_________ (</code> || volume remains quiet) |-| 1010 || 0Ah || <code>\/\/\/\/\/</code> || |-| 1011 || 0Bh || <code>\""""""""" (¯¯¯¯¯¯¯¯¯</code> || volume remains high) |-| 1100 || 0Ch || <code>//////////</code> || |-| 1101 || 0Dh || <code>/""""""""" (¯¯¯¯¯¯¯¯¯</code> || volume remains high) |-| 1110 || 0Eh || <code>/\/\/\/\/\</code> || |-| 1111 || 0Fh || <code>/_________ (</code> || volume remains quiet)|}

This register receives data from the CPC keyboard (or joystick), for more information read the chapter about the [[Programming:Keyboard_scanning|CPC Keyboard Matrix]].  This register can be also used as output port by setting bit 6 of the PSG control register to 1 (that would allow to use the six data pins of the joystick connector to output data to external hardware).

== Mono and Stereo Output ==When using the The [[Aleste 520EX]] (russian CPC's external stereo jack, channel A clone) is output to the righta special case: it has a Yamaha YM2149F chip, channel C is output left, and channel with SSG Port B is output to both left and right, in that case channel B is output through a bigger resistor to prevent that this channel appears loader than the othersbeing used as 8bit printer port data.

== D/A converter table Noise Generator ==These are the 16-bit values used in Arkos Tracker. They are more accurate than the datasheet you can find, as they were tested electronically by Grim and Zik directly from a real CPC:

ay3 manual show different valuesAccording to [https:2 steps down = half values down//github.com/mamedev/mame/blob/master/src/devices/sound/ay8910.h MAME]: The input to the shift register is bit0 XOR bit3. Bit0 is the output. This was verified on AY-3-8910 and YM2149 chips.

However, the algorithm is described in detail in the [[Media:Microchip ay8930.pdf|AY-8930 datasheet]]. And it disagrees with MAME, the input to the shift register is bit0 XOR bit2. And it seems bit1 is the output. [[File:AY38910A noise block diagram.png]] <br> == D/A converter table ==These are the 16-bit values used in Arkos Tracker. They are more accurate than the datasheet you can find, as they were tested electronically by Grim and Zik directly from a real CPC: 0, 231, 695, 1158, 2084, 2779, 4168, 6716, 8105, 13200, 18294, 24315, 32189, 40757, 52799, 65535 For the record, these are [https://groups.google.com/g/comp.sys.sinclair/c/-zCR2kxMryY Matthew (Gasman) Westcott measurements] (normalised) on its ZX Spectrum: 0, 0.0105, 0.0154, 0.0216, 0.0314, 0.0461, 0.0635, 0.1061, 0.1319, 0.2163, 0.2973, 0.3908, 0.5129, 0.6371, 0.8186, 1 The datasheet show different values: 2 steps down = half values down. Thus, the theoretical formula is f(x) = 2 ^ ((x - 15) / 2) with x between 0 1 and 15.

ETO once started testing the output levels (to be fair, with a multimeter only) and it was very close to the theoretical value based on the data sheet and how the CPC mixes the channels.See [https://www.cpcwiki.eu/forum/technical-support/amstrad-cpc-volume-decibel-table/ Discussion on the forum] Volume 0 is indeed silent. It is not just logarithmic attenuation where maximum attenuation of a channel is just very quiet and not silent. [https://forums.nesdev.org/viewtopic.php?p=236734#p236734 Source] <br> == Mono and Stereo Output ==When using the CPC's external stereo jack, the stereo output causes channel A of the PSG to be heard on the left, channel C to be heard on the right and channel B to be heard in the middle. [http://winape.net/help/sound.html Source] In that case, channel B is output through a bigger resistor to prevent that this channel appears louder than the others. Otherwise (when using the built-in speaker), all three channels are mixed at the same intensity. This signal appears to be also sent to the Tape output line also, so a connected Data Recorder could be used to record CPC music also. <br> == BASIC Sound Test == You can test the PSG sound channels by typing simple SOUND commands in BASIC. You should hear a 440Hz sound for 10 seconds at full volume for each of these commands:  SOUND 1,440,1000,15 should produce sound in the left speaker. (channel A) SOUND 2,440,1000,15 should produce sound in both speakers. (channel B) SOUND 4,440,1000,15 should produce sound in the right speaker. (channel C) <br>

Much like the [[CRTC]] chip, the PSG consists of a few simple functional blocks consisting of counters, equality comparators and some fairly simple logic. Careful studies of the chip output prove that the chip '''counts up''' from 0 until the counter becomes '''greater or equal''' to the period, at which point the output flips and the counter resets to 0. (This means that shortening the period can cause an immediate flip if the phase counter is already past the new period value.) This is an important difference when the program is rapidly changing the period to modulate the sound. This is worthwhile noting, since the datasheets say that the chip counts down. Also, note that period =0 is the same as period = Datasheet 1. This is mentioned in the YM2203 datasheet. However, this does NOT apply to the Envelope period. In that case, period =0 is half as period =1. [https://github.com/mamedev/mame/blob/master/src/devices/sound/ay8910.cpp Source] (Does this last sentence apply only to the SSG or to the PSG as well?) The tones, the noise, and envelope are never halted. All of them are continually active whether or not they're connected to an audible output. Things that have been verified not to halt things: [https://forums.nesdev.org/viewtopic.php?p=236745#p236745 Source]* Volume 0 does not halt tone or noise* Tone disable bit does not halt tone* Setting all 3 noise disable bits does not halt noise* Clearing all 3 channel volume envelope bits does not halt envelope* Period value of 0 does not halt any of these (treated as period 1 in all cases) <br> == Schematics == The PSG is driven by an external clock at 1MHz provided by the [[MediaGate Array]].The AY chip has an internal clock divider by 8 which means that it works internally at 125KHz, outputting 125,000 samples per second for each channel. The BC2 and A8 pins are always equal to 1 as they are connected to +5V.The /A9 pin is non-existent on the AY-3-8912 model. On the Amstrad CPC 6128 chassis diagram, we can see how the 3 channels of the PSG are mixed to the stereo jack (with channel B being split in half between the left and right output). And the 3 channels being mixed in equal parts to mono for the speaker and tape port. [https:Ay3//www.cpcwiki.eu/imgs/4/4a/CPC6128_Schematic.png Source] <br> == Chip Variants == === IC models used in CPC === These are the ones known to be used in the CPC by looking at pictures of CPC mainboards. All should operate almost identically. * GI AY-891x3-8912 [https://www.pdfcpcwiki.eu/imgs/c/cc/CPC464_PCB_Top_%28Z70378_MC0046A%29.jpg Source]* GI AY-3-8912A [https://www.cpcwiki.eu/imgs/f/f1/CPC6128_PCB_Top_%28Z70290_MC0020B%29.jpg Source]* Microchip AY-3-8912 [https://www.cpcwiki.eu/imgs/c/cf/AmstradCPC464_Z70375_MC0044D_GA40010_PCB_Top.jpg Source]* Microchip AY38912/P [https://www.cpcwiki.eu/imgs/5/5e/CPC464Plus_MC0122B_2700-016P-3_PCB_Top.jpg Source] === Other Variants === The PSG chip family is composed of 3 variants:* the AY-3-8910, with two 8-bit I/O ports and a 40-pin package* the AY-3-8912, with one 8-bit I/O port and a 28-pin package* the AY-3-8913, with no I/O port and a 24-pin packageIn addition to the CPC, these chips were also used in the [[KC Compact]], [[ZX Spectrum]], [[MSX]], [[Oric-1/Atmos|Oric]], [[EG2000 Colour Genie]], [[Vectrex]], [[Intellivision]] and in the Mockingboard expansion for the [[Apple II]]. There are also PSG clones: Toshiba T7766A, Winbond WF19054, JFC 95101 and File KC89C72. [https://wiki.agiri.ninja/sound_chip_clones:index Source] Yamaha produced the SSG (Software-controlled Sound Generator) chip family (YM2149F, YM3439, YMZ294, YMZ284, YMZ285) which is a quasi-clone of the PSG. The main difference is that the envelope counter on the PSG has 16 steps. On the SSG it has twice the steps, happening twice as fast. This chip equips the [[Atari ST]], [[Aleste 520EX]] and [https://www.msx.org/wiki/Yamaha_YM2149 some MSX computers]. It is also used in the [[PlayCity]] expansion. The SSG has also been integrated as a component inside some of the arcade soundchips of the Yamaha OPN family. That's why you can find it in the [[Neo-Geo]] as a component inside the YM2610 soundchip. And the same is true for the OPN3 soundchip of the [[Play2CPC]] expansion. The chip is clocked differently depending on the computer: ZX Spectrum: 1773400 Hz ; Pentagon: 1750000 Hz ; MSX: 1789772 Hz ; CPC: 1000000 Hz ; Oric: 1000000 Hz ; Atari ST: 2000000 Hz. The EPSG (AY-3-891x datasheet8930), used in the Covox Sound Master soundcard on PCs, is a register-compatible evolution of the AY-3-8910:* The pulse width can be changed from square to 8 other duty cycles* There are 3 independent envelope generators, 1 for each channel* The amplitude control is more accurate (5-bit instead of 4-bit)* The tone period setting is more accurate (16-bit instead of 12-bit)* The noise period setting is more accurate (8-bit instead of 5-bit)* The noise tone can be changed by applying an AND and OR mask to the output === Competitors === The PSG chip competed with the DCSG (Digital Complex Sound Generator) chip family (SN76489, SN94624, TMS9919) by Texas Instruments. The DCSG has similar sounding features except that it does not have any envelope control and that its noise generator has its own dedicated channel. === Replacing the AY-3-8912 in the CPC with an AY-3-8910(A) === In case that the AY-3-8912 needs to be replaced in the CPC it can become a hurdle these days to get a real AY-3-8912 especially for an acceptable price.  Instead of the original AY-3-8912 it's possible to use an AY-3-8910(A) instead with the help of a small adapter board. An open source adapter board can be found here: https://github.com/etomuc/CPC-AY-3-8910-to-8912-adapter For tips regarding the desoldering of ICs see this Wiki page: [[IC Repair]] <br>

[[Category:Music and sound| ]][[Category:Video contents]][[Category:CPC Internal Components]]