Changes
6502
,On NMOS, DF is unchanged when entering an interrupt of any kind. This can cause unexpected bugs in the interrupt handler if Decimal Mode is on when an interrupt occurs. On CMOS, DF is automatically cleared on interrupt. Upon returning from an interrupt, the processor restores the status register from the stack, including DF.
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* On NMOS, when adding a carry to the MSB of an address, a fetch occurs at a garbage address. On CMOS, the last byte of the instruction is refetched.
* On NMOS, when doing a fetch-modify-store instruction (INC, DEC, ASL, LSR, ROL, ROR), garbage is stored into the location during the "modify" cycle... followed by the "real" store cycle which stores the correct data. On CMOS, a second fetch is performed instead of a garbage store.
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CPU 6502 Detailed Block Diagram.jpg|Detailed Diagram
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== Chip Variants ==
* The 6502 core inside the [[NES]] is missing the Decimal Mode feature.
* The 6507 CPU, used in the Atari VCS, has only 13 address lines. So it can only address 8KB instead of 64KB. It also lacks the IRQ and NMI interrupt lines.
* The 6510 CPU, used in the Commodore 64, is a 6502 with an additional AEC pin that the VIC-II uses to kick the CPU off the bus. It also includes a 6-bit I/O port that occupies addresses 0 and 1.
* Similarly, the 6502C used in Atari 8-bit computer range, adds an additional HALT pin. The 6502C is otherwise a regular NMOS 6502, not to be confused with the CMOS 65C02.
* The CMOS 65C02 fixed multiple bugs of the original NMOS 6502, but also removed access to all illegal instructions. And it added some extra instructions. In fact, there are multiple implementations of the 65C02 (WDC 65C02, WDC 65C02S, Rockwell R65C02, CSG 65CE02, ...), each with its own variant of the instruction set.
* The HuC6280, used in the PC-Engine gaming console, is an improved version of the CMOS 65C02.
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* The NOP instruction takes 2 full-cycles. This is the minimum amount of cycles an instruction can take.
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