Changes
== What does it do? ==
The Gate Array is responsible for the display (colour palette, resolution, horizontal and vertical sync), bus arbitration, interrupt generation and memory arrangement.
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== Bus arbitration == == Interrupt management generation ==
Interrupts on the CPC are created by the Gate Array based on settings from the CRTC. The Gate Array has an internal counter R52 (the R is for Raster) that counts from 0 to 51, incrementing after each HSYNC signal.
