Changes
ASIC
,/* Vectored Interrupt */
Bits2..1 of the interrupt vector provided by the ASIC to the CPU are as follows: 00 = DMA chan 2, 01 = DMA chan 1, 10 = DMA chan 0, 11 = DMA raster.
Bit0 of the IVR register controls whether DMA channel interrupts are automatically cleared.
Interrupts are prioritized in a fixed sequence. The raster interrupt has the highest priority, followed by DMA channels 2 down to 0 respectively.
