Changes
CRTC
,/* Datasheets */
CRTC pin CUDISP is not connected to the Gate Array, so it has no effect on a barebone CPC or Plus machine.
However, this signal is present on provided to the expansion port. And it is used by the [[PlayCity]] and [[Play2CPC]] expansions.
== DISPTMG ==
CRTCs 1 and 2 have a fixed VSYNC width value of 16. VSYNC width can be configured with Register 3 on CRTCs 0, 3 and 4.
The bit 0 of port B of the PPI changes to 1 as soon as the VSYNC signal is produced by the CRTC.
== The 6845 Registers ==
|11||Cursor End Raster||xxx00000||0||Sets last raster row of character that cursor is on to invert
|-
|12||Display Start Address (High)||xx000000||48||On Amstrad Plus, bit7 of the printer port is controlled by bit3 of CRTC Reg. 12 R12 (ie. bit11 of Display Start Address)
|-
|13||Display Start Address (Low)||00000000||0||Allows you to offset the start of screen memory for hardware scrolling, and if using memory from address &0000 with the firmware.
|1||0||-||-
|-
|1||1||Read from selected internal 6845 register||Read only Only
|-
|}
|1||0||Read Status Register||Read Only
|-
|1||1||Read from selected internal 6845 register||Read only Only
|}
|1||0||-||-
|-
|1||1||Read from selected internal 6845 register||Read only Only
|-
|}
|1||0||Read from selected internal 6845 register||Read Only
|-
|1||1||Read from selected internal 6845 register||Read only Only
|-
|}
'''Notes'''
* On type 0 The CRTC is not connected to the CPU's RD and 1WR pins, so the CRTC is not aware of the CPU bus I/O direction. Therefore, if a Write Only register is read frominstruction is used on a write register of the CRTC, "0" then a data is returnedsent to the CRTC.
* CRTC type 4 On types 0 and 1, if a Write Only register is the same as read from, "0" is returned. * CRTC type types 3. The registers also repeat as they do on and 4 are identical in every way, except for the type 3unlocking mechanism, split-screen and 8-bit printer port functionalities specific to the ASIC.
* See the document "Extra CPC Plus Hardware Information" for more details.
=== Horizontal and Vertical Sync (R3) ===
*Bits 7..4 define Vertical Sync Width. If 0 is programmed this gives 16 lines of VSYNC.
*Bits 3..0 define Horizontal Sync Width. If 0 is programmed no HSYNC is generated.
*Bits 7..4 are ignored. Vertical Sync is fixed at 16 lines.
*Bits 3..0 define Horizontal Sync Width. If 0 is programmed no HSYNC is generated.
*Bits 7..4 are ignored. Vertical Sync is fixed at 16 lines.
*Bits 3..0 define Horizontal Sync Width. If 0 is programmed this gives a HSYNC width of 16.
*Bits 7..4 define Vertical Sync Width. If 0 is programmed this gives 16 lines of VSYNC.
*Bits 3..0 define Horizontal Sync Width. If 0 is programmed this gives a HSYNC width of 16.
=== Interlace and Skew (R8) ===
*Bits 7..6 define the skew (delay) of the CUDISP signal (00 = Non-skew ; 01 = One-character skew ; 10 = Two-character skew ; 11 = Non-output).
*Bits 5..4 define the skew (delay) of the DISPTMG signal (00 = Non-skew ; 01 = One-character skew ; 10 = Two-character skew ; 11 = Non-output).
*Bits 1..0 define the interlace mode (00 = No Interlace; 01 = Interlace Sync; 10 = No Interlace; 11 = Interlace Sync and Video).
*Bits 7..2 are ignored.
*Bits 1..0 define the interlace mode.
All the other bits read as 0 and don't have any function.
=== R10/R11 on ASIC/Pre-ASIC and R10/R11 ===
The cursor raster registers R10/R11 act as status registers when read on Types 3 & 4. They behave as normal cursor raster registers upon write.
|(C9=R9 and C0=R0) or (C9=0 and C0=0 to R0-1)
|}
=== Reading from CRTC registers on ASIC/Pre-ASIC ===
On CRTC Types 3 and 4, only the 3 least significant bits of the selected register number are considered to read a register according to the following table:
{|{{Prettytable|width: 700px; font-size: 2em;}}
|'''Nb'''||'''Register'''||'''Definition'''
|-
|0||R16||Light Pen Address (High)
|-
|1||R17||Light Pen Address (Low)
|-
|2||R10||Cursor Start Raster
|-
|3||R11||Cursor End Raster
|-
|4||R12||Display Start Address (High)
|-
|5||R13||Display Start Address (Low)
|-
|6||R14||Cursor Address (High)
|-
|7||R15||Cursor Address (Low)
|}
Therefore, as an example, reading register 4 will give the same result as reading register 12 or 20.
<br>
|''Used for interlace and CRTC cursor blinking''
|}
No matter its type, the CRTC never buffers its counters.
The only value that is saved in a buffer in the CRTC is the video pointer because it is reloaded at each line start.
<br>
== Datasheets ==
* [[Media:hd6845.hitachi.pdf|HD6845S (Hitachi) (]] aka type Type 0)]]* [[Media:UM6845-UMC.pdf|UM6845 (UMC) (aka type 0)]]aka Type 0* [[Media:Um6845r.umc.pdf|UM6845R (UMC) (]] aka type Type 1)]]* [[Media:Mc6845.motorola.pdf|MC6845 (Motorola) (aka type 2)]] aka Type 2 [[Media:Mc6845.pdf|Other datasheet version]]* [[Media:CPC_Plus_Asic_Schematic.GIF|AMS40489 (Amstrad)]] aka Type 3* [[AMS40226 (Amstrad)]] aka Type 4*[[Media:CRTC-5-HD6345.pdf|HD6345 (Hitachi) (]] aka type Type 5)]] - Upgraded pin-compatible CRTC chip with advanced functionalities [https://thecheshirec.at/2024/05/07/un-crtc6345-sur-amstrad-cpc/ Upgrading the CPC to HD6345]
== Unused clones ==
* [[CM607P ]] a Bulgarian clone made in Pravetz factory]* [[EF6845P ]] by Thomson Semiconductors]* [[UM6845E ]] by UMC]* [[SY6845EA ]] by Synertek* [[F68B45P]] by Freescale
* CRTC6545 (MOS, Rockwell, Synertek) is pin-compatible with the 6845 and only has minor differences
* [https://github.com/hoglet67/BeebFpga/blob/dev/src/common/mc6845.vhd BeebFpga] [https://github.com/MiSTer-devel/Amstrad_MiSTer/blob/master/rtl/UM6845R.v MiSTer] [https://opencores.org/websvn/filedetails?repname=System09&path=%2FSystem09%2Ftrunk%2Frtl%2FVHDL%2Fcrtc6845.vhd OpenCores] Verilog/VHDL implementations of the 6845
* [http://www.grimware.org/doku.php/documentations/devices/crtc CRTC documentation from Grimware]
* [http://quasar.cpcscene.net/doku.php?id=assem:crtc Quasar CRTC documentation (in french)]
* [https[Media://cpcrulez.fr/coding_CRTC-Paradox.htm Dossier CRTC Rupture(Gozeur/Paradox).pdf]]
* [[Media:Dossier CRTC(Ramlaid Mortel).pdf]] Les entrailles du CRTC
* [https://thecheshirec.at/tag/crtc6845/ Leçons CRTC (CheshireCat)]
*[[Synchronising with the CRTC and display]] : technic and details on the relationship between Gate Array and CRTC.
[[Category:Hardware]] [[Category:CPC Internal Components]] [[Category:Electronic Component]] [[Category:Programming]] [[Category:Datasheet]] [[Category:Graphic]]
