Changes
/* Gate Array Register 2 - Video Mode, ROM enable, LEDs */
|#DFXX||%xx0xxxxx xxxxxxxx||[[Upper ROM Bank Number]] (bank 3 = Aleste Bootmenu)|| - ||Write
|-
|#EEXX||%xxx0xxx0 xxxxxxxx||Aleste USART [[8251 USART chip]] (RS232/Mouse) Data|| ? Read ||Write
|-
|#EFXX||%xxx0xxx1 xxxxxxxx||Aleste USART [[8251 USART chip]] (RS232/Mouse) Control/Status|| ? Read ||Write
|-
|#F4XX||%xxxx0x00 xxxxxxxx||[[8255]] PIO Port A (PSG/8253 Timer/Real-Time Clock data)||Read||Write
|-
|#FA7E||%xxxxx0x0 0xxxxxxx||Floppy Motor Control (for [[765 FDC]])|| - ||Write
|-
|#FABC||%xxxxx0x0 10xxxx00||Aleste EXTPORT with CS53: Forward PPI Port A to 8253 Timer 0|| - ||Write
|-
|#FABD||%xxxxx0x0 10xxxx01||Aleste EXTPORT with CS53: Forward PPI Port A to 8253 Timer 1|| - ||Write
|-
|#FABE||%xxxxx0x0 10xxxx10||Aleste EXTPORT with CS53: Forward PPI Port A to 8253 Timer 2|| - ||Write
|-
|#FABF||%xxxxx0x0 10xxxx11||Aleste EXTPORT with CS53: Forward PPI Port A to 8253 Control|| - ||Write
|-
|#FABF||%xxxxx0x0 10xxxxxx||Aleste EXTPORT|| - ||Write
|}
== Ext Port (Port FABFh) ==
{|{{Prettytable|width: 700px; font-size: 2em;}}
|''bit''||Action
|-
|7||not used|-|6||not used|-|5||if 0, then AY is accessed when read/write to 8255 port A, if 1 then real-time clock is accessed with read/write to 8255 port A. When real-time clock is selected, bits 2..0 of PPI port C are used to define real-time clock operation. DS bit 2, AS bit 1, R/W bit 0. So combinations are 2, write address, 4 write data, 5 read data.
|-
|5-4||Enable PPI Port A usage* 0 = PSG (Sound Chip; default, as in CPC) (With PPI.Port C: BC1/BDIR)* 1 = Reserved (would access both PSG and 8253 timertogether)* 2 = RTC (Real-Time Clock) (With PPI. Any IPort C: Bit2=DS, Bit1=AS, Bit0=R/O W. So combinations are 2, write address, 4 write then accesses 8253 with data comming from 8255 port A. Bit A0, 5 read data)* 3 = 8253 (Baudrate/Future Timer) (With address lines A0 and A1 of I/O port defines 8253 = registerselection)
|-
|3||force video to black
|}
== Aleste Gate Array (aka Patasonic's Multiport) (Port 7Fxxh) ==
Aleste "Gate Array" is similar in functionality to the Gate-Array in the CPC/Plus.
{|{{Prettytable|width: 700px; font-size: 2em;}}
|''Data bit 7''||''Data bit 6''||Action
|-
|0||0||Gate Array Register 0 - Pen Palette index write
|-
|0||1||Gate Array Register 1 - Pen ink writePalette data
|-
|1||0||Gate Array Register 2 - Mode, Rom enable, Leds
|-
|1||1||Gate Array Register 3 - Used by mapperRAM banking
|-
|}
=== Gate Array Register 0 - Palette Index ===
{|{{Prettytable|width: 700px; font-size: 2em;}}
|''bit''||Action''Value''
|-
|7..6||Must be 0|-|6||(select register 0)
|-
|5||not used
|-
|4..0||If set to 1Palette Index (00h..0Fh=Ink 0-15, border is selected10h=Border, 11..1Fh=same as 10h)|}Selects the palette index (to be used by next write to Palette Data). {|{{Prettytable|width: 700px; font-size: 2em;}}|''Depth''||''Normal Inks (as on CPC)''||''Secondary Inks (Aleste FUTURE Feature)''
|-
|1 bit||0..1||2..3|-|2 bit||0..3||4..7|-|4 bit||0..15||Pen indexN/A (uses 0..15 too)
|}
=== Gate Array Register 1 - Palette Data ===
The number is converted by IC D62.
* When MAPPER is not set, the number is equivalent to the CPC's Gate-Array colour value, but this is looked up in IC D62 and converted into a 2-bit per element R,G,B for the aleste video hardware.
* '''Note''' - The CPC supports 3 intensities per color (0%, 50%, 100%), the Aleste supports four intensities (0%, 33%, 66%, 100%). In the CPC-style 27-color mode, the Aleste uses only the dark intensities (0%, 33%, 66%), this gives it a proper ratio (66% being twice 33%), the downside is that the 64-color mode appears brighter - so one may need to adjust brightness on the monitor whenever switching between 27-color and 64-color modes. === Gate Array Register 2 - Video Mode, ROM enable, LEDs ===
{|{{Prettytable|width: 700px; font-size: 2em;}}
|''bit''||Action
|-
|7||01
|-
|6||10
|-
|5||CAPS LED
|}
=== Gate Array Register 3 - RAM banking (in CPC-style MAPMOD=0) ===
Controls RAM Banking, similar to the Gate Array on CPC6128 (or, more specific, similar to the 16L8 PAL IC which assists the CPC6128s Gate Array).
'''Actually''', it seems to work more like an [[Inicron RAM-Box]] (which isn't fully compatible with the dk'tronics style [[Standard Memory Expansions]]).
=== Gate Array Register 3 - RAM banking (in Aleste's special MAPMOD=1) ===
Four I/O ports control the mapper:
The decoding of the I/O port for the mapper uses bit 15 of the I/O address in the same way as the Aleste "Gate Array".
Address Bit 9,8 define which page.
To avoid writing to the Aleste "Gate-Array" , Data bits 7 and 6 of the data must be 1.
The remaining bits define the RAM block/configuration to use.
In Aleste mapper mode, writing to the mapper changes the RAM for one page.
07h AMSDOS (bytes in 8000h..BFFFh in the Aleste's 64K EPROM)
All other values 01h..02h, 04h..06h, 08h..FFh do select BASIC, too.
The BOOTMENU is an aleste specific ROM bank. BASIC and AMSDOS are 1:1 same as in CPC6128. The BIOS (lower ROM bank) is almost same as in CPC6128 (only the Startup Message and Printer handling are modified). For details, see:
* [[Media:AlesteBiosDisassembly.txt]] - Disassembly of differences between CPC6128 and Aleste BIOS
* [[Media:AlesteBootmenuRomBank3.asm]] - Original source code for BOOTMENU (Upper ROM Bank 3)
== PPI 8255 ==
|-
|}
Ext Port (Port FABFh) controls whether PSG, RTC, or Timer is selected.
* For info on Baudrate/Future Timer see [[8253 chip]].
* For info on Real Time Clock see [[PC compatible RTC chip]].
=== PPI Port B (Port F5xxh) ===
The built-in RS232 port can be used to connect a serial mouse.
* See [[Serial RS232 Mouse]] for details on the protocol
[[Category:Non CPC Computers]][[Category:Clones]]
